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为什么有verilog验证文件不是模块形式的？

[英]Why there are verilog verification files not in the form of module?

原文 2015-06-09 08:49:06 1 1 verilog/ verification

Why are there Verilog verification files not in the form of a module ?为什么有些 Verilog 验证文件不是module形式的？ The files I see start with just initial begin , and some file names use the .inc extension.我看到的文件以initial begin ，有些文件名使用.inc扩展名。

1 个解决方案

It is common to include files of arbitrary content into Verilog modules.将任意内容的文件包含到 Verilog 模块中是很常见的。 This is done using the `include compiler directive, as described in IEEE Std 1800-2012, section "22.4 `include ":这是使用`include编译器指令完成的，如 IEEE Std 1800-2012, section "22.4 `include "中所述：

The file inclusion (include) compiler directive is used to insert the entire contents of a source file in another file during compilation.文件包含（include）编译器指令用于在编译期间将源文件的全部内容插入到另一个文件中。 The result is as though the contents of the included source file appear in place of the `include compiler directive.结果就像包含的源文件的内容出现在 `include 编译器指令的位置。

It can be useful for sharing common code between different modules: parameters, define macros, tasks, functions, etc.它可用于在不同模块之间共享通用代码：参数、定义宏、任务、函数等。

In general, the .inc file extension is not special.一般来说， .inc文件扩展名并不特殊。 It may be a convention used by certain simulation tools.它可能是某些模拟工具使用的约定。