综合后FPGA如何在设计中推断VHDL状态

Question

I am unable to identify the VHDL constants in the FPGA after synthesis. After Post synthesis I am able to identify my logic in the netlist. But not for the Constant parameters. Did really constants will infer in the FPGA or not ?

Answer 1

Synthetizer simplifies your design.
Synthetizer reduces logic equations to remove constants and use less LUTs.
So your constants are included in the LUTs.

An example, when you write :

constant C_CONSTANT : std_logic_vector(3 downto 0) := "1111"
...
if a = C_CONSTANT then
  b <= '1';
else
  b <= '0';
end if;

The logic equation is :

   b = eq(a(0),C_CONSTANT(0)).eq(a(1),C_CONSTANT(1)).eq(a(2),C_CONSTANT(2)).eq(a(3),C_CONSTANT(3))  
=> b = (a(0).C_CONSTANT(0) + /a(0)./C_CONSTANT(0)).(a(1).C_CONSTANT(1) + /a(1)./C_CONSTANT(1)).(a(2).C_CONSTANT(2) + /a(2)./C_CONSTANT(2)).(a(3).C_CONSTANT(3) + /a(3)./C_CONSTANT(3))
=> b = (a(0).1 + /a(0).0).(a(1).1 + /a(1).0).(a(2).1 + /a(2).1).(a(3).1 + /a(3).0)
=> b = a(0).a(1).a(2).a(3)

The constant has faded away by logic simplification. The synthetizer does exactly the same to gave you this result :
with this truth table for the LUT :