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如何将VHDL项目放在Spartan 6 FPGA上

[英]How to put VHDL project on Spartan 6 FPGA

I am working on a project in VHDL that will be placed onto the spartan 6 fpga. 我正在研究一个VHDL项目,该项目将被放置在斯巴达6 fpga上。 The code is ready but I am not sure how to proceed with getting it onto the fpga. 代码准备就绪,但我不知道如何继续将它放到fpga上。

I have access to another project and noticed that this project has a Microblaze processor (.xmp) file in it and a ucf file that defines all the "NET" interfaces. 我可以访问另一个项目,并注意到该项目中有一个Microblaze处理器(.xmp)文件和一个定义所有“NET”接口的ucf文件。

Eventually I will be using the FPGA and add-on board connector to communicate with a piece of hardware but I need moving everything onto the FPGA. 最终,我将使用FPGA和附加板连接器与一块硬件进行通信,但我需要将所有内容移到FPGA上。

Some resources and tutorials would be great, especailly how to get the microblaze processor into my project, that is if I even need it. 一些资源和教程会很棒,特别是如何将微型光泽处理器纳入我的项目,即如果我需要它。

Thanks 谢谢

Update: I started simulation of my project and have an error. 更新:我开始模拟我的项目并出错。

Line 214: statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition 第214行:语句不可合成,因为它在NOT(时钟边沿)条件下不保持其值

I get this in one of my project files in ana if statement that says 我在ana if语句中的一个项目文件中得到了这个

if rising_edge(clk) then
-- other if statements that assign output values
end if

I tried changing the code around but it no longer works if I do. 我尝试改变代码,但如果我这样做则不再有用。

Not sure what the error means exactly. 不确定错误意味着什么。

The UCF file should contain both constraints to which pins that belong to each of your signals as well as any timing conditions. UCF文件应包含属于每个信号的引脚以及任何时序条件的约束。 The "easiest" way is to read the guide for writing such files, or to use the built-in tool that helps you to get them right “最简单”的方法是阅读编写此类文件的指南,或使用内置工具帮助您使其正确

Here is the Xilinx guide. 是Xilinx指南。

Thiis is one of the most important constraints: Thiis是最重要的约束之一:

TIMESPEC “TSidentifier”=PERIOD “TNM_reference” period {HIGH | TIMESPEC“TSidentifier”= PERIOD“TNM_reference”期间{HIGH | LOW} [high_or_low_time ] INPUT_JITTER value; LOW} [high_or_low_time] INPUT_JITTER值; (cut from the above file) (从上面的文件中删除)

One of the best tutorials for new VHDL developers is the short tutorial "Intro to Spartan 3E FPGA and VHDL, by Mike Field. You can download the PDF and all the source code from his GitHub account , or browse the chapters for the book on his website . 新VHDL开发人员的最佳教程之一是Mike Field的简介“Spartan 3E FPGA和VHDL简介”。您可以从他的GitHub帐户下载PDF和所有源代码,或者浏览他的书中章节。网站

You'll go from a simple Hello World equivalent in FPGA, to using DCMs and generating VGA signals, in a matter of hours. 您将在几小时内从简单的Hello World等效FPGA转换为使用DCM并生成VGA信号。

Mike uses both Papilio One and Digilent Basys2 boards in the book, but you can easily adapt the examples to any board you're using. Mike在书中使用了Papilio One和Digilent Basys2板,但您可以轻松地将示例调整到您正在使用的任何板上。 You just need to adjust the UCF file accordingly. 您只需要相应地调整UCF文件。 The fact that he's using Spartan-3 and you're using Spartan-6 shouldn't make any difference. 他使用Spartan-3而你使用Spartan-6这一事实应该没有任何区别。

The UCF, or User Constraints File, is the file that tells your FPGA its connections to the external world. UCF或用户约束文件是告诉FPGA与外部世界的连接的文件。 The UCF is highly dependent on your particular hardware, as each board has a different set of pins. UCF高度依赖于您的特定硬件,因为每个板都有一组不同的引脚。 You're probably using a board provided by one of the popular manufacturers, so you just have to check the documentation for your particular hardware. 您可能正在使用其中一个受欢迎的制造商提供的电路板,因此您只需查看特定硬件的文档即可。

After finding the original UCF file for your particular board, it's recommended that you delete all lines that you're not using (meaning: all nodes that are not connected to anything within your vhdl code), otherwise the compiler will raise warnings or errors. 在找到特定主板的原始UCF文件后,建议您删除所有未使用的行(意味着:所有未连接到vhdl代码中的任何节点的节点),否则编译器将引发警告或错误。

This should be enough to get you started. 这应该足以让你入门。

ps: if you don't have any specific reason to use MicroBlaze, you can safely ignore it for now. ps:如果你没有任何具体的理由使用MicroBlaze,你现在可以放心地忽略它。

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