从系统verilog测试台驱动verilog中的内部信号

Question

How can you drive internal signals of a DUT verilog code from testbench?

Consider this following example:

module dut(input bit clk); 
    logic [7:0] data;
endmodule : dut

module top; 
    bit clk;
    dut dut1(.*); 
    assign dut.data = '0; // this doesn't work.
endmodule 

Answer 1

Cross module references do work. The catch, though, is that any signal in the DUT will already be driven. You need to override that driver. Force and release are the usual way of doing this but you can also just use a stronger driver strength.

The default drive strength is "Strong" so the only thing stronger is "supply".

For your example:

assign (supply0, supply1) data = '0;

Strictly speaking, the supply1 is unnecessary as you are only driving zero. However, it eliminates the surprise you might get if you ever need to change your code to drive '1'.