如何在 Chisel3 中使用多输入逻辑门？

Question

I am implementing a Carry Lookahead Adder using Chisel3. In order to shorten latency, I need to use multi-input logic gate.

However, even if I write code like

io.out:= a | b | c | d | e

, the generated verilog code will be like

assign _T = a | b
assign _T_1 = _T | c
assign _T_2 = _T_1 | d
assign io_out = _T_2 | e

which uses 4 OR gates, and leads to 4x gate delay.

I am wondering that is there a way to generate multi-input logic gates? Such as

assign io_out = a | b | c | d | e

or

or (io_out, a, b, c, d,e)

Answer 1

One work around would be to construct a multi input OR gate class where you can define how you want the connections to be made so that the translations happen the way you want.