Verilog 中的 BCD 加法器（带门）

Question

My goal is coding a BCD adder in Verilog with gates. I have some issues:

1- How can I select bits from first "four bit adders" outputs. My sum is S . After I used S in first adder, can I select bits like S[0] or is there another way?

2- How can I specify inputs, especially if I have a module for four_bit_adder and it takes one element like A (4 bits)? I tried to specify some bits, but I couldn't handle it.

For example, A[3] and A[1] needed to be 0 or 1 regarding the some situations, but my module takes one element.

My trial is below:

`include "four_bit_adder.v"

module bcd_adder(S,A,B,Cin);

input [3:0]A,B;
input Cin;
output [3:0]S;

wire [2:0]connectors;

//four_bit_adder(S,Cout,A,B,Cin);

four_bit_adder F_A1(S,Cout,A,B,Cin);

and(connectors[0],S[3],S[2]);

and(connectors[1],S[3],S[1]);

or(connectors[2],connectors[1],connectors[0],Cout);

//four_bit_adder F_A2();

endmodule

Answer 1

I added a Cout output to your bcd_adder , driven by your or gate. I changed connectors to [1:0] .

I created a wire for the binary sum ( sumb ), driven by your 1st 4-bit adder. This is different from your BCD sum S . sumb is connected to the A input of the 2nd 4-bit adder.

For the B input to the 2nd adder, I concatenate 4 bits like this:

{1'b0,Cout,Cout,1'b0}

Here is the completed module:

module bcd_adder(S,Cout,A,B,Cin);

input [3:0]A,B;
input Cin;
output [3:0]S;
output Cout;

wire [1:0]connectors;
wire [3:0]sumb;
wire coutb;
wire cout2; // floating

four_bit_adder F_A1 (sumb,coutb,A,B,Cin);
four_bit_adder F_A2 (S,cout2,sumb,{1'b0,Cout,Cout,1'b0},1'b0);

and(connectors[0],sumb[3],sumb[2]);
and(connectors[1],sumb[3],sumb[1]);
or (Cout,connectors[1],connectors[0],coutb);

endmodule