如何将调试消息传递给 SystemVerilog 中的宏

Question

I'm attempting the following SystemVerilog:

`define DEBUG (ARG) \
`ifdef DEBUG_ON \
  $display ARG;
`endif

module my_mod;
logic a;
logic [1:0] b;

assign a = 1'b0;
assign b = 2'b01;

`DEBUG(("a=%x, b=%b", a, b))
endmodule

VCS gives me the following compile error:

Error-[SE] Syntax error
  Following verilog source has syntax error :
  "/media/psf/Home/projects/dep2/hw/rtl/dep_dc/dep_dc_cs.sv", 254 (expanding 
  macro): token is '('
        `DEBUG(("a=%x, b=%b", a, b))
              ^

#0, DEBUG : "<my_file>":21
full expansion of macro (DEBUG), error at line 1
=>(ARG) 
  `ifdef DEP_DEBUG_ON
  ...

According to this answer: How to emulate $display using Verilog Macros?

This seems like the correct syntax to me. Can someone spot anything wrong?

Answer 1

So I found it apparently, the compiler doesn't like spaces between the macro definition and arguments:

`define DEBUG(ARG) \
`ifdef DEBUG_ON \
  $display ARG;
`endif

Works.