[英]How to achieve signal connection depends on macro's value (`if FOO==X) in SystemVerilog?
I hope to connect instance signals depends on a MACRO's value: 我希望连接实例信号取决于MACRO的值:
moduleA u_MODULE_A (
...
`if FOO == 0
.a (siga),
.b (sigb),
.c (sigb),
`elif FOO == 1
.a (sigb),
.b (siga),
.c (sigc),
`elif FOO == 2
.a (sigc),
.b (sigb),
.c (siga),
...
`endif
...);
The moduleA
has more than 100 ports and the FOO
macro has 15 possible values at the moment (would add more). moduleA
有100多个端口,而FOO
宏此刻有15个可能的值(将添加更多)。
The current solutions I have are: 1. Create additional macro for each value: FOO_0, FOO_1, ... 2. Use generate to instantiate moduleA multiple times. 我目前拥有的解决方案是:1.为每个值创建额外的宏:FOO_0,FOO_1,... 2.使用generate多次实例化moduleA。
Both the solutions would have a lot of work for maintain the code. 两种解决方案在维护代码方面都需要大量工作。
Does anyone have better solutions? 有谁有更好的解决方案?
If the macro could work like that, wouldn't that also be a lot of work to maintain? 如果宏可以像这样工作,那还不算很多工作吗?
How about: 怎么样:
localparam FOO = `FOO;
generate
case (FOO)
0: begin
assign a = siga;
assign b = sigb;
assign c = sigc;
end
1: begin
assign a = sigb;
assign b = siga;
assign c = sigc;
end
...
endcase
endgenerate
moduleA u_MODULE_A (
...
.a (a),
.b (b),
.c (c),
...);
声明:本站的技术帖子网页,遵循CC BY-SA 4.0协议,如果您需要转载,请注明本站网址或者原文地址。任何问题请咨询:yoyou2525@163.com.