How to achieve signal connection depends on macro's value (`if FOO==X) in SystemVerilog?

Question

I hope to connect instance signals depends on a MACRO's value:

moduleA u_MODULE_A (
    ...
`if FOO == 0
    .a (siga),
    .b (sigb),
    .c (sigb),
`elif FOO == 1
    .a (sigb),
    .b (siga),
    .c (sigc),
`elif FOO == 2
    .a (sigc),
    .b (sigb),
    .c (siga),
 ...
 `endif
 ...);

The moduleA has more than 100 ports and the FOO macro has 15 possible values at the moment (would add more).

The current solutions I have are: 1. Create additional macro for each value: FOO_0, FOO_1, ... 2. Use generate to instantiate moduleA multiple times.

Both the solutions would have a lot of work for maintain the code.

Does anyone have better solutions?

Answer 1

If the macro could work like that, wouldn't that also be a lot of work to maintain?

How about:

localparam FOO = `FOO;
generate
  case (FOO)
   0: begin
    assign a = siga;
    assign b = sigb;
    assign c = sigc;
   end 
   1: begin
    assign a = sigb;
    assign b = siga;
    assign c = sigc;
   end
   ...
  endcase
endgenerate

moduleA u_MODULE_A (
 ...
 .a (a),
 .b (b),
 .c (c),
 ...);