[英]Concatenate signal names in systemverilog using macro
I am trying to concatenate two strings in systemverilog/verilog to create a signal names. 我试图在systemverilog / verilog中连接两个字符串以创建信号名称。 In my below code snippet, the lhs side seem to work fine, but the rhs side doesn't. 在我下面的代码片段中,lhs方面似乎工作正常,但rhs方面却没有。 The tool gives an error "bitemp has not been declared yet". 该工具给出错误“尚未声明bitemp”。
If i pass a hardcorded value say "0" to "clno" parameter, then it works for both lhs and rhs. 如果我将硬编码的值传递给“ clno”参数,请说“ 0”,那么它对lhs和rhs都适用。
enter code here
`define strcat_assign_macro(lhs_prestr,lhs_poststr,rhs_prestr,rhs_poststr,clno) \
assign lhs_prestr``clno``lhs_poststr = rhs_prestr``clno``rhs_poststr;
module tempmod;
wire a0temp,b0temp;
wire a1temp,b1temp;
wire a2temp,b2temp;
assign b0temp =1'b1;
genvar i;
generate
for(i = 0; i < 3; i++)
begin
`strcat_assign_macro(a,temp,b,temp,i)
end
endgenerate
initial begin
$display (a0temp );
end
endmodule
Macros get expanded before parsing any Verilog/SystemVerilog syntax. 在解析任何Verilog / SystemVerilog语法之前,宏将得到扩展。 Use an array of wires. 使用电线阵列。
Since `defines are expanded before compilation, you are getting those errors. 由于定义会在编译前扩展,因此您会遇到这些错误。
One way to avoid that is to use a script to automate the define usage and use the same define in the Verilog file. 避免这种情况的一种方法是使用脚本来自动化定义用法,并在Verilog文件中使用相同的定义。
Here is a sample shell script, which I have made for this purpose. 这是我为此目的制作的示例shell脚本。 It is a basic script, but I think is sufficient to get you the idea. 这是一个基本的脚本,但我认为足以使您明白这一点。
#!/bin/csh
set b='`'
set a=`egrep -n "^ *${b}strcat_assign_macro" $2 | cut -d: -f1`
set line=`egrep -n "${b}strcat_assign_macro" $2 | cut -d: -f2`
foreach i (`seq $1`)
set c=`expr $a + $i`
sed -i "${c}i${line}" temp.ip
sed -i "${c}s/^\(.*\), *[0-9]* *)/\1, ${i})/g" temp.ip
end
Here is the file before & after script. 这是脚本前后的文件。
// Before
karan
shah
`strcat_assign_macro(b, temp, a, temp, 0)
maheshbhai
// ./temp.sh <Extra Define Lines> <FileName>
./temp.sh 2 input.v
// After
karan
shah
`strcat_assign_macro(b, temp, a, temp, 0)
`strcat_assign_macro(b, temp, a, temp, 1)
`strcat_assign_macro(b, temp, a, temp, 2)
maheshbhai
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