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面罩如何在凿子中使用集合 memory?

[英]How the mask can be used in aggregate memory in chisel?

I'm tring to use aggregate memory in chisel.我想在凿子中使用聚合 memory。

As recommended in github, https://github.com/ucb-bar/chisel3-wiki/blob/master/Chisel-Memories.md如 github、 https://github.com/ucb-bar/chisel3-wiki/blob/master/Chisel-Memories.md中推荐的

My code looks like follows:我的代码如下所示:

class Interface(val w:Int) extends Bundle{
  val a: UInt = UInt(w.W)
  val b: UInt = UInt(w.W)
  val c: UInt = UInt(w.W)
}

val mem = Mem(16,new Interface(4))

Then I use mask as below:然后我使用掩码如下:

mem.write(io.addr, inter, mask)

where the type of 'inter' is Interface, the type of 'mask' is Vec[Bool]其中'inter'的类型是Interface,'mask'的类型是Vec[Bool]

The following error is given:给出以下错误:

Cannot prove that mytest.Interface <:< chisel3.Vec[_].

I have done some searching, found that mask can only be used when the memory is defined by Vec.我做了一些搜索,发现掩码只能在 memory 由 Vec 定义时使用。

There is any solution to make this work?有什么解决方案可以使这项工作?

As you noted, mask can only be used when the data type of the memory is a Vec .如您所述,仅当 memory 的数据类型为Vec时,才能使用mask

You didn't describe how exactly you'd like the mask to correspond to the interface, but I'm assuming you would have a Vec of size 3, one bit for each a , b , and c .您没有描述您希望mask如何与接口相对应,但我假设您将拥有一个大小为 3 的Vec ,每个abc一个位。

The simplest solution is to just use Vec(3, UInt(4.W)) :最简单的解决方案是只使用Vec(3, UInt(4.W))

val mem = Mem(16, Vec(3, UInt(4.W)))

If you then want to read and write as if it were actually made of Interface , you can cast:然后,如果您想像实际上由Interface制成一样读写,则可以强制转换:

mem.write(io.addr, inter.asTypeOf(Vec(3, UInt(4.W)), mask)

These casts are a little verbose, you can create type aliases to make the code more concise and maintainable:这些转换有点冗长,您可以创建类型别名以使代码更简洁和可维护:

val w = 4
val memType = Vec(3, UInt(w.W))
val intfType = new Interface(w)

val mem = Mem(16, memType)
mem.write(io.addr, inter.asTypeOf(memType), mask)

val read: Interface = mem.read(io.addr).asTypeOf(intfType)

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