我有一个 Verilog 代码，问题是我需要与 B_G2 同时将 C 位到 go HIGH 并在 else 语句中完成

Question

The issue is that I need C bit to go HIGH at the same time as B_G2 and that it is done at the else statement.

Here is the code that I have so far:

module lightcontrol(clk, R,C, A_CAR, B_CAR, lightsA, lightsB, cnt);
     
    `define A_G2 3'b000
    `define A_Y 3'b001
    `define B_G1 3'b010
    `define B_G2 3'b110
    `define B_Y 3'b101
    `define A_G1 3'b100
     
    `define RED 3'b100
    `define YELLOW 3'b010
    `define GREEN 3'b001
     
    input clk;            
    input A_CAR;          
    input B_CAR;          
    input R ;            
     
    output [2:0] lightsA;      
    output [2:0] lightsB;      
    output [3:0] cnt;
    output C;
          
    reg [3:0] cnt = 0;
    reg [2:0] state;           
    reg C = 0;
     
    always @(posedge clk)
 
        begin   
            if (R==0 && C==1)
                begin 
                    if((state == `B_G2)&&(A_CAR == 1'b1)) 
                        state=`B_Y;
                        C=0; 
                end
 
            else if ((R==1 &&C==0) | (R==1 && C==1))
                 state = `A_G2;
            else
                case(state)
                    `A_G2: state = B_CAR ? `A_Y : `A_G2;
                    `A_Y: state = `B_G1;
                    `B_G1: 
                        begin 
                            state = `B_G2;
                            C=1;
                        end
                    `B_G2: state = A_CAR ? `B_Y : `B_G2 ;
                    `B_Y: state = `A_G1 ;
                    `A_G1: state = `A_G2 ;
                endcase
        end
        assign lightsA = ((state == `A_G2)|(state == `A_G1)) ? `GREEN: (state == `A_Y) ? `YELLOW : `RED;
        assign lightsB = ((state == `B_G2)|(state == `B_G1)) ? `GREEN: (state == `B_Y) ? `YELLOW : `RED;
endmodule

Answer 1

You should use non-blocking assignments

Instead of initializing variables like you are doing with reg C = 0 you should use a reset. Other than this, In order to get the event you need to determine what are the conditions necessary to run that code.

Immediately you see that it requires C == 0 , R == 0 to run the case (to advance the state). And the event you are interested requires state to be B_G1 , you can go to state == B_G1 from state == A_Y , and you can reach to state == A_Y if you are in state A_G2 and the input B_CAR is set. Finally (initially) you go to state A_G2 when R == 1 . Maybe better to understand in a waveform.

(powered by wavedrom )

{signal: [
  {name: 'clk', wave: 'p....'},
  {name: 'R', wave: '10...'},
  {name: 'C', wave: 'x0..1'},
  {name: 'state', wave: 'x2345', data:['A_G2', 'A_Y', 'B_G1', 'B_G2']},
  {name: 'B_CAR', wave: 'x1xxx'},
]}