gcc, makefile does not link correctly

Question

I have this makefile:

CC=gcc
CFLAGS= -c -Wall -std=c99 -ggdb

all: plan

plan: plan.o graph.o
    $(CC) $(CFLAGS) plan.o graph.o -o plan

plan.o: plan.c graph.h
    $(CC) $(CFLAGS) plan.c

graph.o: graph.c graph.h
    $(CC) $(CFLAGS) graph.c

run: all
    ./plan

when I run make, gcc give me the message "linker input file unused because linking not done", what does it mean by that?

Answer 1

The -c option means:

Compile or assemble the source files, but do not link. The linking stage simply is not done. The ultimate output is in the form of an object file for each source file.

You should not use that option when building.

See gcc man

Update

For the plan target, do not use the CFLAGS:

plan: plan.o graph.o
    $(CC) -Wall -std=c99 -ggdb plan.o graph.o -o plan