Makefile: gcc line does not show up

Question

If i run the line with make target_name :

$(CC) $(CFLAGS) $(OPTS) $(TARGET) &> gcc_log_file

i get the following result in the gcc_log_file : nothing it is strange because if i type make -n target_name , the line is well expanded.

I could add '-v' to gcc but this will be quite ugly, i just want the GCC line to be expanded...

I tried the following workarounds

@echo "$(OBJ) $$($(CC) $(CFLAGS) $(OPTS) $(TARGET))" &> gcc_log_file

@printf "$(OBJ) %s\n" $$($(CC) $(CFLAGS) $(OPTS) $(TARGET)) &> gcc_log_file

the CC line is executed, $(OBJ) is expanded but not the CC line...

I should precise explicitly that I want to do this inside the makefile, because I don't want to log in the gcc_log_file lines that are not produced by gcc...My makefiles are quite complexes.

any hints?

note that my gcc is a special one, based on gcc 5.2, but i reckon this behavior is the same.

Answer 1

What you see is normal. Whatever COMMAND is, COMMAND &> FILE executes COMMAND and redirects its standard and error outputs to file FILE . But in your case COMMAND is a compilation command and if there are no errors or warnings your compiler does not print anything on stdout or stderr. So, what is redirected to your log file is nothing at all.

You can check this very easily:

$ echo 'int main(void) { return 0; }' > foo.c
$ gcc -o foo foo.c
$

See? No output of any kind that you could send to a log file.

While if you make -n it is make (not your compiler) that echoes the recipe it would pass to the shell without the -n option. If you want to log your recipes you must echo them yourself in another recipe with, for instance, the echo command that sends its shell-expanded parameters to the standard output:

target: prerequisites
    @echo "COMMAND" >> log_file
    COMMAND

Example:

foo: foo.c
    @echo '$(CC) $(CFLAGS) -o $@ $<' >> log_file
    $(CC) $(CFLAGS) -o $@ $<

If you do not want to type the same command twice you can declare a make variable:

COMPILATION = $(CC) $(CFLAGS) -o $@ $<

foo: foo.c
    @echo '$(COMPILATION)' >> log_file
    $(COMPILATION)

Or, all at once:

COMPILATION = $(CC) $(CFLAGS) -o $@ $<
ECHOCOMPILE = echo '$(COMPILATION)' >> log_file; $(COMPILATION)

foo: foo.c
    @$(ECHOCOMPILE)

(remove the leading @ if you want make to echo the recipe when passing it to the shell).

Pay attention to the variable assignment operator ( = ). Do not use the simple assignment operator ( := ), it would not work for reasons that are out of scope this question.

Note that, by default, make echoes the recipes (if you do not prepend a @ ). So, you could as well redirect the output of make:

$ cat Makefile
foo: foo.c
    $(CC) $(CFLAGS) -o $@ $<
$ make &> log_file
$ cat log_file
gcc -o foo foo.c