Overflow status register flag when shifting bits

Question

当您在装配中执行“逻辑左移” ， “逻辑右移”或“算术右移”时， 两个补码溢出标记的含义是什么？

Answer 1

This may depend upon the microprocessor and you need to check the respective manual for the instruction set. If you read the AVR instruction set manual, it explains what happens to the status register bits.

For LSL , V (two's complement overflow) is determined by:

V: N ⊕ C (For N and C after the shift)
N: Set if MSB of the result is set; cleared otherwise.
C: Set if, before the shift, the MSB of Rd was set; cleared otherwise.

V is the exclusive OR of the negative bit (highest order bit in the 8-bit value after shift) and the carry bit. Semantically, it means that the upper two bits of your value, before the shift, had opposite parity.

For LSR , V (two's complement overflow) is determined by:

V: N ⊕ C (For N and C after the shift)
N: 0
C: Set if, before the shift, the LSB of Rd was set; cleared otherwise.

In this case, since N is 0 , then V is simply the complement of C . It's bit value is therefore the opposite of whatever the least significant bit value was for the 8-bit value before the shift. Semantically, if it's set, it means that the upper two bits of your value, before the shift, had opposite parity.

For ASR , V (two's complement overflow) is determined by:

V: N ⊕ C (For N and C after the shift)
N: Set if MSB of the result is set; cleared otherwise.
C: Set if, before the shift, the LSB of Rd was set; cleared otherwise.

Semantically, ASR treats the 8-bit value as if it were signed in that it preserves the highest order (sign) bit. So N indicates that the value is a negative 8-bit value (before and after the shift, since it's preserved). The V bit will be set if the value shifted is negative and it was even (lowest order bit was clear) before the shift, and it will be set if the shifted value is positive and it was odd (lowest order bit was set) before the shift. Otherwise, V will be clear.