make: *** No rule to make target `gcc', needed by `Employee.o'. Stop

Question

I am quite new to makefile. Could you please help me correcting with the below makefile:

I have created a Employee class. Manager class is derived from Employee class. And Link class has references to both Employee and Manager class.

Error:

  make: *** No rule to make target `gcc', needed by `Employee.o'.  Stop.

Makefile :

  CC = gcc
  TOP=/usr/local/share/cimple
  ROOT= $(PEGASUS_ROOT)
  ##BINDIR= ${PEGASUS_HOME}/bld/bin
  TARGET = ${PEGASUS_HOME}/lib/libEmployee.so
  LIBRARY_FLAGS = -L${PEGASUS_HOME}/lib
  ##PROVIDERROOT = $(PEGASUS_ROOT)/../providers
  INSTANCE_PROVIDER_OBJECTS = Employee.o Manager.o Link.o module.o repository.o Employee_Provider.o Manager_Provider.o Link_Provider.o

  COMPILE_FLAGS = -W -Wall -g -fPIC
  LINK_FLAGS = -W -Wall -g -shared
  EXTRA_INCLUDES = -I$(PROVIDERROOT) -I${PEGASUS_ROOT}/src

  LIBRARIES = pegcommon pegprovider
  DYNAMIC_LIBRARIES = -lpegcommon -lpegprovider


  include $(TOP)/mak/config.mak

  MODULE=1
  SHARED_LIBRARY=Employee

  ##
  ## Define source files for compile and link
  ##

  SOURCES += Employee.cpp
  SOURCES += Manager.cpp
  SOURCES += Link.cpp
  SOURCES += module.cpp
  SOURCES += repository.cpp
  SOURCES += Employee_Provider.cpp
  SOURCES += Manager_Provider.cpp
  SOURCES += Link_Provider.cpp

  ##
  ## Module defined as Pegasus C++ interface
  ##
  CIMPLE_PEGASUS_MODULE=1
  DEFINES += -DCIMPLE_PEGASUS_MODULE

  LIBRARIES += cimplepegadap
  LIBRARIES += cimple

  include $(TOP)/mak/rules.mak


  ${TARGET} : ${INSTANCE_PROVIDER_OBJECTS} Makefile ${CC} ${LINK_FLAGS}   ${LIBRARY_FLAGS} -o ${TARGET} ${INSTANCE_PROVIDER_OBJECTS} ${DYNAMIC_LIBRARIES}


  Employee.o : Employee.cpp Makefile Employee.h ${CC} ${COMPILE_FLAGS} ${EXTRA_INCLUDES} -c Employee.cpp

  Manager.o : Manager.cpp Makefile Manager.h ${CC} ${COMPILE_FLAGS} ${EXTRA_INCLUDES} -c Manager.cpp

  Link.o : Link.cpp Makefile Link.h ${CC} ${COMPILE_FLAGS} ${EXTRA_INCLUDES} -c Link.cpp

  repository.o : repository.cpp Makefile repository.h ${CC} ${COMPILE_FLAGS} ${EXTRA_INCLUDES} -c repository.cpp

  module.o : module.cpp Makefile module.h ${CC} -DCIMPLE_PEGASUS_MODULE ${COMPILE_FLAGS} ${EXTRA_INCLUDES} -c module.cpp

  Employee_Provider.o : Employee_Provider.cpp Makefile Employee_Provider.h ${CC} ${COMPILE_FLAGS} ${EXTRA_INCLUDES} -c Employee_Provider.cpp

  Manager_Provider.o : Manager_Provider.cpp Makefile Manager_Provider.h ${CC} ${COMPILE_FLAGS} ${EXTRA_INCLUDES} -c Manager_Provider.cpp

  Link_Provider.o : Link_Provider.cpp Makefile Link_Provider.h ${CC} ${COMPILE_FLAGS} ${EXTRA_INCLUDES} -c Link_Provider.cpp

I am getting the above mentioned error.Any help would be much appreciated! Thanks in advance!

Answer 1

Correct the makefile to include an "Enter" and "Tab" character before the command actually making the target, eg like this for the Employee.o:

Employee.o : Employee.cpp Makefile Employee.h<ENTER>
<TAB> ${CC} ${COMPILE_FLAGS} ${EXTRA_INCLUDES} -c Employee.cpp

The general syntax of Makefile targets is:

targetname: dependencies <ENTER>
<TAB>command to build targetname

See eg here for a more detailed explanation: http://mrbook.org/tutorials/make/

Answer 2

the tool GNU Make needs tabulations to consider some text as a recipe. Furthermore, you may be interested in pattern rules. You could replace all the *.o generation rules with a generic one (based on pattern matching):

%.o: %.cpp %.h
    ${CC} ${COMPILE_FLAGS} ${EXTRA_INCLUDES} -c $@

This rule will generate any *.o files from the corresponding source/header files. Easy to maintain ! note the tab before ${CC}...