Interface SystemVerilog with a verilog module

Question

I believe that SystemVerilog is a much higher level of abstraction in coding. Is it possible to interface a SystemVerilog module with a verilog module? Are they any aspects that should be kept in mind when trying to integrate them?

Answer 1

Verilog and SystemVerilog are the same language - that is, anything you know about Verilog exists in SystemVerilog. From a synthesis point of view, you will sill be connecting bit of signals with other bits of signals. Its just that with SystemVerilog, you will have more advanced ways of declaring those signals, and many more operators to manipulate those signals.

Without knowing any SystemVerilog, I suggest that you learn it by itself before trying to integrate older Verilog modules with SystemVerilog modules. It will be difficult to explain what to look out for.

One thing that does carry over from Verilog to SystemVerilog is the concept of nets(wires) and variables(regs). Make sure you have a clear understanding of that, plus the new semantics SystemVerilog adds. I have a small article on it. Verilog only allowed wires to pass through ports and did not enforce directions. SV allows variables to pass through ports (meaning variables on both sides of the port connection) but strongly enforces directionality.

Answer 2

Yes, it is possible to interface system verilog module to verilog module. Before that you must have understanding regarding signals (variable) which are used in verilog module.

You have to create interface from which your verilog signals are connected to system verilog module. So, data transfer between verilog and system verilog module is possible.

Here I provide verilog module and system verilog module. Main part of code is interface from which verilog and system verilog module are connected.

verilog module code :

module dff(qn,d,clk,reset);

output qn;
input d,clk,reset;
reg qn;

always@(posedge clk,negedge reset)

begin

if (!reset)

begin
qn=1'bx;
end

else if (d==0)
begin
qn=0;
end
else if (d==1)
begin 
qn=1;
end

end

endmodule

System verilog module code :

interface melay_intf(input bit clk);

  logic o,clk,rst,i;

  clocking c1@(posedge clk);
    input o;
    output i,rst;
  endclocking

endinterface

module top;
  bit clk;

  always
    #1 clk = ~clk;

  melay_intf i1(clk);

  dff d1(.o(i1.o),.clk(i1.clk),.rst(i1.rst),.i(i1.i));

  melay_tes(i1.tes);

endmodule

program melay_tes(melay_intf i1);

  initial
    #100 $finish;

  initial
    begin
      i1.rst <= 0;
      #4 i1.rst <= 1;
      #4 i1.rst <= 0;

      i1.i = 1;
          #2 i1.i = 0;
          #2 i1.i = 1;
          #2 i1.i = 0;
          #2 i1.i = 1;
          #2 i1.i = 0;


      repeat(10)
        begin
          i1.i = 1;
          #2 i1.i = $urandom_range(0,1); 
        end
    end

  initial
    $monitor("output = %d   clk = %d    rst = %d    i = %d",i1.o,i1.clk,i1.rst,i1.i);
  initial
    begin
      $dumpfile("mem.vcd");
      $dumpvars();

    end
endprogram

Here important part is interface and in it I used clocking block for synchronization purpose. Here clocking c1@(posedge clk); so all signals which are mention inside the clocking block which are i,o,rst.All this signal change its value at every posedge of clk signal.

Here dff d1(.o(i1.o),.clk(i1.clk),.rst(i1.rst),.i(i1.i)); Important thing that you find in top module I made connection between verilog signals and system verilog signals.

You can find verilog module name is "dff". I took the instance of dff verilog module and made the connection. Here i1.o,i1.clk,i1.rst,i1.i is system verilog signals which are connected to o,clk,rst,i signals of verilog module of with dot convention.

Answer 3

System verilog (SV) is mainly used for design verification, so the thing is that the DUT (Device Under Test) is written in verilog mainly because verilog can be synthesized mostly. SV is then used to write verification environment for that DUT. Interfaces are needed in between to connect the SV with the DUT which is verilog. Separate file is written is SV to specify what are the different connection between the two files. This file say INTERFACE file is included in all the separate blocks which need those connections. You can refer the IEEE standard https://standards.ieee.org/getieee/1800/download/1800-2012.pdf for further information on SV.