Verilog wrapper for SystemVerilog

Question

I'm trying to create a Verilog wrapper for a VS counter.

I have written the following SystemVerilog code for the counter:

//counter.sv

interface counter_if(input clk, rstn);
    logic [3:0] out;
    modport dut(input clk,rstn, output out);
endinterface : counter_if

module counter(counter_if.dut cnt);

    always @ (posedge cnt.clk) begin
        if (! cnt.rstn)
            cnt.out <= 0;
        else
            cnt.out <= cnt.out + 1;
    end
endmodule

Also, I've written the following Verilog code:

//wrapper file
module counter_wrapper(clk,rstn,out); 
    input clk; 
    input rstn;
    output reg [3:0] out; 
        
    counter_if cnt (.clk(clk), .rstn(rstn));
    counter cnt0 (
        .cnt(cnt)
    );
endmodule 

When I compile it, I get the following error for the Verilog file:

Error: (vlog-2110) Illegal reference to interface "cnt"

So I changed the interface call to the following:

//wrapper file
module counter_wrapper(clk,rstn,out); 
    input clk; 
    input rstn;
    output reg [3:0] out; 
        
    counter_if cnt (.clk(clk), .rstn(rstn));
    counter cnt0 (
        .cnt(cnt.dut)
    );
endmodule 

Now the design compiles, but when simulating the following error comes up:

• Error: (vsim-3044) Usage of 'cnt.dut' inconsistent with 'modport' object.

Any insight will be highly appreciated!

Answer 1

Standard-compliant Verilog code cannot instantiate a SystemVerilog interface. You'll need to either use an SV wrapper or remove the interface and replace it with normal module ports. Verilog can connect to SV just fine (in most tools) with regular module ports.

//counter.sv
module counter (
    input logic clk,
    input logic rstn,
    output logic [3:0] out
);

    always @ (posedge clk) begin
        if (!rstn)
            out <= 0;
        else
            out <= out + 1;
    end
endmodule