SystemVerilog typedef equivalent in Verilog

Question

Is there any construct I can use in Verilog that would be equal to SystemVerilog's typedef ?

I know that in SV I can create my own names for type definitions and use it when building up complicated array definitions. I know that typedef doesn't exist in Verilog standard (ie Verilog-1995). But is it possible to somehow bypass it?

Answer 1

Almost all current tools that support Verilog today also support the typedef construct in SystemVerilog. I would spend your time figuring out how to move to SystemVerilog rather than trying to workaround the lack of it in Verilog. The closest thing you could use in Verilog would be a `define statement.

Answer 2

SystemVerilog具有用户定义的数据类型，而Verilog没有。