What is the difference between makefile and sh file. sh(shell script file) file also can work at the place of makefile(means we can do same thing using shell file like makefile can do) then what is difference between them. there is any execution difference or any standard where we have to use makefile and sh file.
one Example of this to compile a hello.c file with Makefile and shell file
shell.sh
param="$1";
CC="gcc"
CFLAGS="-c -Wall";
if [ "$param" == "clean" ];
then
rm -rf hello
else
$CC $CFLAGS hello.c -o hello
fi
./shell.sh
{ will build hello.c file } ./shell.sh clean
{ this will clean the build file } Same thing with Makefile..
CC=gcc
CFLAGS=-c -Wall
hello: hello.c
$(CC) $(CFLAGS) hello.c -o hello
clean:
rm -rf hello
make
{it will build}
make clean
{it will clean build file}
Both files can generate same output. This question because some people use Makefile and some people use shell..
make
automatically checks (based on time stamps) which targets need to be remade and which ones can be left untouched. If you write your own shell script, you'll either have to program this logic yourself or else all your components will be rebuilt when you run your script - even those that haven't changed since the last build.
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