adding a prerequisite results in “nothing to be done for 'all'”

Question

I'm just getting back into the world of Makefiles and have a vexing problem: adding a $*.h prerequisite on a rule for generating the corresponding .o file always results in "nothing to be done". Below is my Makefile in its entirety:

SOURCES := mu.cpp node.cpp test_node.cpp transport.cpp
OBJECT_DIR := ../obj
INCLUDE_DIR := ../include

OBJECTS := $(patsubst %.cpp,$(OBJECT_DIR)/%.o,$(SOURCES))

CC      = g++
DEFS    = 
CFLAGS  = -O3 -Wall
IFLAGS  = -I$(INCLUDE_DIR) -I../tarballs/stk-4.4.4/include

$(OBJECT_DIR)/%.o : %.cpp $(INCLUDE_DIR)/mu.h $(INCLUDE_DIR)/$*.h 
        $(CC) $(CFLAGS) $(IFLAGS) -c $(<) -o $@

all: $(OBJECTS)

clean:
        rm -f $(OBJECT_DIR)/*.o

$(OBJECTS): | $(OBJECT_DIR)

$(OBJECT_DIR):
        mkdir $(OBJECT_DIR)

If I type make all using the above, make always responds with "nothing to be done for 'all'" But if I change the rule that reads:

$(OBJECT_DIR)/%.o : %.cpp $(INCLUDE_DIR)/mu.h $(INCLUDE_DIR)/$*.h 

to

$(OBJECT_DIR)/%.o : %.cpp $(INCLUDE_DIR)/mu.h

(ie, I remove foo.cpp's dependency on ../include/foo.h), then make all responds as expected. The problem with this, of course, is that foo.cpp will not be recompiled if ../include/foo.h has been modified more recently than foo.cpp.

FWIW, I've verified that $(INCLUDE_DIR)/$*.h expands to the proper file name.

I'm pretty sure this is something obvious. Any hints?

Answer 1

Automatic variables like $* are not defined anywhere except in the recipe of the rule. You cannot use them in the prerequisites list.

Why don't you just use the pattern in both cases?

$(OBJECT_DIR)/%.o : %.cpp $(INCLUDE_DIR)/%.h $(INCLUDE_DIR)/mu.h