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wrap Verilog code in chisel

 原文  2014-06-11 03:42:13  2   1    scala/ verilog/ chisel

Question

Is it possible to wrap some verilog code into chisel/scala code? if yes, how can I do this? I need to use some verilog module in chisel.

thank you

Francesco

1 answers

solution1
 4  2014-06-12 22:47:50

You will want to look up the BlackBox construct ( https://chisel.eecs.berkeley.edu/2.2.0/chisel-manual.pdf ) and see if that addresses your question.

The BlackBox will let you describe how Chisel interfaces with your Verilog code. Then, you compile your Chisel design to Verilog. Once you have Chisel's outputted Verilog, you have to manually connect your Chisel Verilog design to your existing Verilog code.

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