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FPGA implement look up table with LUTs

I would like to implement a 8 to 1 multiplexer in FPGA. The inputs of the multiplexers are constants, so I use a look up table instead.

I know that fpgas are made of LUTs. Is there any hardware block that I can use in order to optimize the multiplexer?

Thank you

Not really, unless the each of the 8 "words" you're using is EXTREMELY large and could justify a blockRAM (discussion on when to use a blockRAM here - http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Lut-vs-Block-Ram/td-p/251888 ). If your bus is only 1 bit, or 8 bits wide...just use a case statement. The synthesis & routing stages will take care of converting that "code" into the individual LUTs on the FPGA.

As others have said, ISE is smart enough to infer a mux from your code. You can verify this after running synthesis. Check the Summary in the synthesis report.

If you really want to use LUTs as a good learning exercise, you certainly can do it using a few staged together. Read Understanding the INIT attribute for LUTs to learn how to use the INIT property.

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