Makefile to build C and CPP files

Question

I have been looking for a Makefile to compile a huge project which contains lots of C and C++ files. I have used Eclipse to compile it successfully but I want to go to a standalone Makefile. I found this generic Makefile that works really well with my project except it can only compile C or C++ files but not both in one run...so it fails at Linking time.

The bits of original Makefile that compile for CPP or C:

        SRC_EXT = cpp
        OURCES = $(shell find $(SRC_PATH)/ -name '*.$(SRC_EXT)' -printf '%T@\t%p\n' \
        SOURCES = $(shell find $(SRC_PATH)/ -name '*.$(CPP_EXT)' -o -name '*.$(C_EXT)' -printf '%T@\t%p\n' \
                            | sort -k 1nr | cut -f2-)
        # fallback in case the above fails
        rwildcard = $(foreach d, $(wildcard $1*), $(call rwildcard,$d/,$2) \
                                $(filter $(subst *,%,$2), $d))
        ifeq ($(SOURCES),)
            SOURCES := $(call rwildcard, $(SRC_PATH)/, *.$(SRC_EXT))
        endif
OBJECTS = $(SOURCES:$(SRC_PATH)/%.$(SRC_EXT)=$(BUILD_PATH)/%.o)
DEPS = $(OBJECTS:.o=.d)

I tried to modify it to be:

SRC_EXT = cpp c
SOURCES = $(shell find $(SRC_PATH)/ -name '*.$(CPP_EXT)' -o -name '*.$(C_EXT)' -printf '%T@\t%p\n' \
                    | sort -k 1nr | cut -f2-)
# fallback in case the above fails
rwildcard = $(foreach d, $(wildcard $1*), $(call rwildcard,$d/,$2) \
                        $(filter $(subst *,%,$2), $d))
ifeq ($(SOURCES),)
    SOURCES := $(call rwildcard, $(SRC_PATH)/, *.$(SRC_EXT))
endif

But i'm not sure what to do with the OBJECTS directive to make it work with the multiple extensions:

OBJECTS = $(SOURCES:$(SRC_PATH)/%.$(SRC_EXT)=$(BUILD_PATH)/%.o)

Can anybody help with this please?

Thanks

Answer 1

首先，将.cpp替换为.o ，然后将其余的.c替换为.o 。