What is Eclipse CDT is doing with 'make' under the hood

Question

I'm on Windows 7 and have MinGW/gcc installed. I'm using the Eclipse CDT plugin to compile and build my first simple C programs, and am trying to follow what exactly the plugin is doing under the hood.

I create a new "Hello World!" C project with the following directory structure:

helloworld/
    src/
        helloworld.c

Where helloworld.c is:

#include <stdio.h>
#include <stdlib.h>

int main(void) {
    puts("Hello World!");
    return EXIT_SUCCESS;
}

So I created a Run Configuration in Debug Mode (as opposed to "Release Mode", not a "Debug Configuration" in typical Eclipse parlance!) and ran my app, and it works beautifully, printing "Hello World!" to the Eclipse console.

Now I'm looking on my file system and the file/project structure is like so:

helloworld/
    src/
        helloworld.c
    Debug/
        src/
            helloworld.d
            helloworld.o
            subdir.mk
        helloworld.exe
        makefile
        objects.mk
        source.mk

I assume that running my Run Configuration in Eclipse (hence compiling/building/running helloworld inside Eclipse) created everything under Debug . Furthermore I assume that helloworld.d and helloworld.o are compiled binaries, and that helloworld.exe is the packaged executable containing those binaries and everything they'red linked to ( stdio and stdlib ). I also assume makefile is the actual Make file (buildscript), and that the *.mk files are somehow inputs to that buildscript. So, for starters, if any of those assumptions are wrong, please begin by correcting me!

When I open makefile I see this:

################################################################################
# Automatically-generated file. Do not edit!
################################################################################

-include ../makefile.init

RM := rm -rf

# All of the sources participating in the build are defined here
-include sources.mk
-include src/subdir.mk
-include subdir.mk
-include objects.mk

ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(C_DEPS)),)
-include $(C_DEPS)
endif
endif

-include ../makefile.defs

# Add inputs and outputs from these tool invocations to the build variables 

# All Target
all: helloworld

# Tool invocations
helloworld: $(OBJS) $(USER_OBJS)
    @echo 'Building target: $@'
    @echo 'Invoking: Cross GCC Linker'
    gcc  -o "helloworld" $(OBJS) $(USER_OBJS) $(LIBS)
    @echo 'Finished building target: $@'
    @echo ' '

# Other Targets
clean:
    -$(RM) $(EXECUTABLES)$(OBJS)$(C_DEPS) helloworld
    -@echo ' '

.PHONY: all clean dependents
.SECONDARY:

-include ../makefile.targets

Please note: I am not looking for someone to explain to me how Make works, I can RTFM for that ;-)

I am just trying to understand what it would take to compile, build and run helloworld from the command-line, outside of Eclipse. What command line invocations would I need to accomplish this, and why? Once I see that, combined with perusing Make docs, I should be able to fill in the gaps and understand everything that is going on.

Answer 1

That depends a bit on the paths that Eclipse generates in the files source.mk and objects.mk but most likely you need to cd into the Debug folder.

Inside of that, you can then run make all to compile the project.

If Eclipse generated absolute paths, you can use make -f .../path/to/helloworld/Debug/makefile all from anywhere.

Answer 2

The *.o files are the object file(s) created by compilation. these files are typically build by a command like:

    Gcc -ansi -Wall -pedantic -c helloworld.c -o helloworld.o

(apologies foe capitalization of gcc, my iPad insists on correct my typing)

The *.exe is the actual executable, which may or may not contain the library functions. This depends on static versus dynamic linking. The executable is created typically by:

    Gcc helloworld.o -o helloworld.exe 

The *.d files are dependency files, built by gcc attempting to determine dependencies between files, typically built with the following command

    MAKEDEPEND = gcc -M $(CPPFLAGS) -o $*.d $<

(Rule taken from make online documentation).

So,to answer your final question, to compile from the command line, a command like:

    Foo gcc -ansi -WAll -pedantic helloworld.c -o helloworld.exe

Should do the trick for you. Note, the flags to the compiler are the minimum that I like to use, you will probably have a different set of switches.

Hopes this help, T