VHDL for loop limit on clock cycle

Question

I have the following for loop in my code:

for index in 0 to a'length-1 loop
  result(index) := a(index) xor bb(index) xor carry_in;
  carry_in := (carry_in and (a(index) or bb(index))) or
              (a(index) and bb(index));
    end loop;

It accepts a signal a for 32 bits. So the loop has 32 iterations. I was wondering where the bottleneck is in how many iterations can be run until the FPGA cannot run this code anymore. I am able to synthesize the code, but when I increase the clock frequency higher than 48MHz, the .bit stream file cannot be read anymore by the FPGA. Any frequency lower than 48 MHz is fine.

Is there a kind of bottleneck in the amount of iterations in the for loop on the how long the clock cycle may be?

Answer 1

The count of loop iterations, the size of an FPGA and it's max. clock frequency are not really connected...

The synthesis translates your loop into several stages (your examples has 32). The more stages you generate, the more FPGA resources are used. So you can fill up a whole FPGA with one loop.

The max. clock frequency depends on the longest path between two flip flops (aka critical path). For example a critical path of 18 ns is equal to a Fmax of circa 50 MHz (see critical path, setup/hold times, static timing analysis for more details on this subject). When your loop produces a long critical path and does not insert pipeline flip flops, then Fmax will decrease. You can also look into your synthesis report for Fmax analysis or other indicators like: Levels of Logic.

If a FPGA does not accept a bit file, then you are uploading the wrong bit file. I triggered this by myself. I choose the wrong FPGA size and pinout for a Spartan-3E. This caused the USB/JTAG loader to crash and hangup my USB port and then my PC :(.