VHDL map for each bit in a vector

Question

Whats the best way to perform a port map for each bit in a vector? Say I have a vector representing a series of buttons, and wish to debounce each one using a bebounce module, how should I go about that?

Right now I have the following, but I believe there should be a better way

entity ButtonDebouncer is
    Port (
        clock : in std_logic;
        buttons : in std_logic_vector(0 to 5);
        --{ more stuff }
    );
end ButtonDebouncer;

architecture Behavioral of ButtonDebouncer is
    signal bufferedButtons : std_logic_vector(0 to 5) := (others => '0');
begin
    c1: entity debounce port map (Clock, buttons(0), bufferedButtons(0));
    c2: entity debounce port map (Clock, buttons(1), bufferedButtons(1));
    c3: entity debounce port map (Clock, buttons(2), bufferedButtons(2));
    c4: entity debounce port map (Clock, buttons(3), bufferedButtons(3));
    c5: entity debounce port map (Clock, buttons(4), bufferedButtons(4));
    c6: entity debounce port map (Clock, buttons(5), bufferedButtons(5));

    --{ Do stuff with debounced buttons }
end Behavioral;

Answer 1

For generate would be a good candidate construct here.

entity ButtonDebouncer is
    Port (
        clock : in std_logic;
        buttons : in std_logic_vector(0 to 5);
        --{ more stuff }
    );
end ButtonDebouncer;

architecture Behavioral of ButtonDebouncer is
    signal bufferedButtons : std_logic_vector(0 to 5) := (others => '0');
begin
    debouncers: for i in 0 to 5 generate
        c1: entity debounce port map (Clock, buttons(i), bufferedButtons(i));
    end generate;
    --{ Do stuff with debounced buttons }
end Behavioral;

Answer 2

Travis' solution is a good starting point.

I would go one step further and implement a debounce module for multiple bits. So you can pass a whole button vector to this module.

entity debounce is
  generic (
    BITS   : POSITIVE
  );
  port (
    Clock   : STD_LOGIC;
    Input   : STD_LOGIC_VECTOR(BITS - 1 downto 0);
    Output  : STD_LOGIC_VECTOR(BITS - 1 downto 0)
  )
end entity;

architecture rtl of debounce is
  -- define 'global' signals here (per instance)
begin
  genDebounce : for i in 0 to BITS - 1 generate
    -- define 'local' signals here (per debounce circuit)
  begin
    -- debounce circuit
  end generate;
end architecture;

Usage:

debButtons : entity work.debounce
  generic map (
    BITS    => buttons'length
  )
  port map (
    Clock   => Clock,
    Input   => Buttons,
    Output  => bufferedButtons
  );