RISC-V Rocket Cache Coherence

Question

For the RISC-V Rocket processor, what kind of write policy do the caches employ (eg Write Back + Allocate, Write Through + No Allocate)? How are the L1 caches kept coherent with the L2 caches in RISC-V?

Answer 1

RISC-V is an ISA (instruction set architecture), not a processor. Thus, the ISA has nothing to say about cache write-back policies or coherency design. Those decisions are left up to the individual processor design teams. In fact, they don't even need to have caches.

The only thing RISC-V has to say about memory is the "memory consistency model". RISC-V uses a fairly relaxed consistency model, and thus it is possible for two RISC-V threads to see two different sequences/interleavings of memory operations (as opposed to "sequential consistency" where all threads see the same interleaving).

---

Edit (now that the question clarifies it is only asking about the Berkeley Rocket processor):

As of 2015 Sept 9, Rocket's L1 cache is write-back+allocate. L1's are kept coherent via snoop requests. Each Rocket core sits on a "Rocket Tile" that contains an L1.

An optional L2 sits outside the Rocket tiles. Rocket tiles arbitrate access to the single L2. The L2 is inclusive and holds all L1 data. However, the L2 may be holding stale data, but if a core requests that data, the L2 will know which L1 holds the current copy of the data and will send a release request as appropriate.