verilog testbench component instantiate using generate

Question

I'm new to verilog and learning. I have a testbench questions. Suppose in Verilog testbench I have 8 instances of a module. Is there a way to instantiate them in the testbench using a generate loop like a module can be declared in the HDL part of the code. For example

module my_test_bench;
reg one_r;
reg two_r;

wire one_w;
wire two_w;

genvar i;
generate
(for i = 0; i < 8; i=i+1)
begin
   DDR3_module uut[i]( .clk(), .rst(), );
end
endgenerate

initial begin
 ... test stimulus
end

end module

Thanks.

Answer 1

Yes, you can. Use the following syntax:

genvar i;
generate
  for (i = 0; i < 8; i = i + 1) begin
    DDR3_module uut (.clk(clk[i]), .rst(rst[i]));
  end
endgenerate

Note that you need vectors for the clk and rst signals for each instance, such as the following preceding declaration lines:

wire [7:0] clk;
wire [7:0] rst;

If you want to drive those directly from within your initial block however, those need to be reg s instead of wire s.