Can I apply 5V logic to JTAG pins of xc95288xl?

Question

I have designed an XC95288xl CPLD board. I have used two 74125 buffers to connect parallel port to the jtag pins of the cpld. Both cpld and 74125 buffers use 3.3V for power. But I wanted to know is this possible to use 5V to power buffers while 3.3 for I/O pins of the CPLD?

XC9500xl family datasheet says IO ports are 5V tolerant, but didn't say anything about jtag pins.

I'm asking this question because if I provide 5V to buffers, they will use 5V TTL on its pins and I'm afraid if it damages the cpld. Also I can't record any implementation on the cpld at the moment (eg programming doesn't work, ISE says could not find the cable, though I have tested the cable carefully)

Answer 1

XC95288XL Datasheet

The datasheet only calls out input and outputs. So the specs are the same for the JTAG signals and for the I/O. They are all relative to VCCIO.

XC9500XL Family Datasheet

Important see this note in the XC9500XL datasheet:

The I/Os on each XC9500XL device are fully 5V tolerant even though the core power supply is 3.3 volts. This allows 5V CMOS signals to connect directly to the XC9500XL inputs without damage. The 3.3V VCCINT power supply must be at least 1.5V before 5V signals are applied to the I/Os.

If 5V is applied to the device while it is powered off or before the VCCINT rail has come up to at least 1.5V it may damage the device. This is mentioned in other places.

Also see:

Xilinx answer