How could I connect a circuit to a FPGA with FPGIO?

Question

I'm trying to make a counter with a sensor, the counter will be in the FPGA to show on a 7 segments, the code does not show error but when I connect the fpgio the counter on the 7 segments turns crazy.

ENTITY prueba IS

GENERIC(pines:POSITIVE:=8);

PORT(

    clk   : IN  STD_LOGIC;
    reset : IN  STD_LOGIC;
    pulsos: INOUT  STD_LOGIC;
    A     : BUFFER STD_LOGIC_VECTOR(0 TO 6);
    B     : BUFFER STD_LOGIC_VECTOR(0 TO 6);
    C     : BUFFER STD_LOGIC_VECTOR(0 TO 6)
    );
END prueba;

ARCHITECTURE test OF prueba IS

SIGNAL un,dec : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL cnt    : UNSIGNED(25 DOWNTO 0);
SIGNAL cnun,cndec,cncen : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN

    pSeq :  PROCESS(clk,reset,pulsos)IS
        BEGIN

IF reset = '1' THEN
                un  <= "0000";
                dec <= "0000";
                cnun<= "0000";
                cndec<= "0000";
                cncen<= "0000";

        ELSIF clk'EVENT AND clk='1' THEN
            IF cnt(25) = '1' THEN
                IF(un="1001")THEN
                    un <="0000";
                    dec<=dec+1;
                        IF(dec="1001")THEN
                        dec<="0000";
                        END IF;
                ELSE
                  un <= un+1;
                END IF;
            cnt <= "00000000000000000000000000";
            ELSE
            cnt<=cnt+1;
            END IF;
END IF;

    IF reset = '1' THEN 
    ELSIF (pulsos='0')THEN
        IF(cnun="1001")THEN
            cnun <="0000";
            cndec<=cndec+1;

            IF(cndec="1001")THEN
                cndec<="0000";
                cncen<=cncen+1;

                IF(cncen="1001")THEN
                    cncen<="0000";
                END IF;

            END IF;

        ELSE
            cnun <= cnun+1;
        END IF;
    END IF;


CASE cnun IS

    WHEN "0000" => A <="0000001";
    WHEN "0001" => A <="1001111";   
    WHEN "0010" => A <="0010010";
    WHEN "0011" => A <="0000110";
    WHEN "0100" => A <="1001100";
    WHEN "0101" => A <="0100100";
    WHEN "0110" => A <="0100000";
    WHEN "0111" => A <="0001111";
    WHEN "1000" => A <="0000000";
    WHEN "1001" => A <="0001100";
    WHEN OTHERS => A <="1111111";
END CASE;

CASE cndec IS

    WHEN "0000" => B <="0000001";
    WHEN "0001" => B <="1001111";  
    WHEN "0010" => B <="0010010";
    WHEN "0011" => B <="0000110";
    WHEN "0100" => B <="1001100";
    WHEN "0101" => B <="0100100";
    WHEN "0110" => B <="0100000";
    WHEN "0111" => B <="0001111";
    WHEN "1000" => B <="0000000";
    WHEN "1001" => B <="0001100";
    WHEN OTHERS => B <="1111111";
END CASE;

CASE cncen IS

    WHEN "0000" => C <="0000001";
    WHEN "0001" => C <="1001111";
    WHEN "0010" => C <="0010010";
    WHEN "0011" => C <="0000110";
    WHEN "0100" => C <="1001100";
    WHEN "0101" => C <="0100100";
    WHEN "0110" => C <="0100000";
    WHEN "0111" => C <="0001111";
    WHEN "1000" => C <="0000000";
    WHEN "1001" => C <="0001100";
    WHEN OTHERS => C <="1111111";

END CASE;

END PROCESS;

END test;

Every change that I make give me an error like this:

Can't infer register for "<name>" at <location> because it does not hold its value outside the clock edge

Answer 1

What causes the error shows up in the first part of the process:

pseq:
    process ( clk, reset, pulsos) is
    begin
        if reset = '1' then
            un  <= "0000";
            dec <= "0000";
            cnun <= "0000";
            cndec <= "0000";
            cncen <= "0000";
        elsif clk'event and clk = '1' then
            if cnt(25) = '1' then
                if un = "1001" then
                    un <="0000";
                    dec <= dec + 1;
                    if dec = "1001" then
                        dec<="0000";
                    end if;
                else
                  un <= un + 1;
                end if;
                cnt <= "00000000000000000000000000";
            else
                cnt <= cnt + 1;
            end if;
        end if;

You have a conditional test for a clock edge in the first elsif, which assigns cnt. Note the following else also assigns cnt without regards to the clock edge. This is not a synthesis eligible form for inferring sequential edge sensitive logic.

There's also the if statement following, which looks of dubious synthesis eligibility:

        if reset = '1' then 
        elsif pulsos ='0' then
            if cnun = "1001" then
                cnun <= "0000";
                cndec <= cndec + 1;
                if cndec = "1001" then
                    cndec <= "0000";
                    cncen <= cncen + 1;
                    if cncen = "1001" then
                        cncen< = "0000";
                    end if;
                end if;
        else
            cnun <= cnun+1;
        end if;
    end if;