[英]How could I connect a circuit to a FPGA with FPGIO?
我正在尝试使用传感器创建一个计数器,该计数器将在FPGA中显示为7段,但代码未显示错误,但是当我连接fpgio时,这7段中的计数器会发疯。
ENTITY prueba IS
GENERIC(pines:POSITIVE:=8);
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
pulsos: INOUT STD_LOGIC;
A : BUFFER STD_LOGIC_VECTOR(0 TO 6);
B : BUFFER STD_LOGIC_VECTOR(0 TO 6);
C : BUFFER STD_LOGIC_VECTOR(0 TO 6)
);
END prueba;
ARCHITECTURE test OF prueba IS
SIGNAL un,dec : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL cnt : UNSIGNED(25 DOWNTO 0);
SIGNAL cnun,cndec,cncen : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
pSeq : PROCESS(clk,reset,pulsos)IS
BEGIN
IF reset = '1' THEN
un <= "0000";
dec <= "0000";
cnun<= "0000";
cndec<= "0000";
cncen<= "0000";
ELSIF clk'EVENT AND clk='1' THEN
IF cnt(25) = '1' THEN
IF(un="1001")THEN
un <="0000";
dec<=dec+1;
IF(dec="1001")THEN
dec<="0000";
END IF;
ELSE
un <= un+1;
END IF;
cnt <= "00000000000000000000000000";
ELSE
cnt<=cnt+1;
END IF;
END IF;
IF reset = '1' THEN
ELSIF (pulsos='0')THEN
IF(cnun="1001")THEN
cnun <="0000";
cndec<=cndec+1;
IF(cndec="1001")THEN
cndec<="0000";
cncen<=cncen+1;
IF(cncen="1001")THEN
cncen<="0000";
END IF;
END IF;
ELSE
cnun <= cnun+1;
END IF;
END IF;
CASE cnun IS
WHEN "0000" => A <="0000001";
WHEN "0001" => A <="1001111";
WHEN "0010" => A <="0010010";
WHEN "0011" => A <="0000110";
WHEN "0100" => A <="1001100";
WHEN "0101" => A <="0100100";
WHEN "0110" => A <="0100000";
WHEN "0111" => A <="0001111";
WHEN "1000" => A <="0000000";
WHEN "1001" => A <="0001100";
WHEN OTHERS => A <="1111111";
END CASE;
CASE cndec IS
WHEN "0000" => B <="0000001";
WHEN "0001" => B <="1001111";
WHEN "0010" => B <="0010010";
WHEN "0011" => B <="0000110";
WHEN "0100" => B <="1001100";
WHEN "0101" => B <="0100100";
WHEN "0110" => B <="0100000";
WHEN "0111" => B <="0001111";
WHEN "1000" => B <="0000000";
WHEN "1001" => B <="0001100";
WHEN OTHERS => B <="1111111";
END CASE;
CASE cncen IS
WHEN "0000" => C <="0000001";
WHEN "0001" => C <="1001111";
WHEN "0010" => C <="0010010";
WHEN "0011" => C <="0000110";
WHEN "0100" => C <="1001100";
WHEN "0101" => C <="0100100";
WHEN "0110" => C <="0100000";
WHEN "0111" => C <="0001111";
WHEN "1000" => C <="0000000";
WHEN "1001" => C <="0001100";
WHEN OTHERS => C <="1111111";
END CASE;
END PROCESS;
END test;
我所做的每个更改都会给我这样的错误:
Can't infer register for "<name>" at <location> because it does not hold its value outside the clock edge
导致错误的原因显示在过程的第一部分:
pseq:
process ( clk, reset, pulsos) is
begin
if reset = '1' then
un <= "0000";
dec <= "0000";
cnun <= "0000";
cndec <= "0000";
cncen <= "0000";
elsif clk'event and clk = '1' then
if cnt(25) = '1' then
if un = "1001" then
un <="0000";
dec <= dec + 1;
if dec = "1001" then
dec<="0000";
end if;
else
un <= un + 1;
end if;
cnt <= "00000000000000000000000000";
else
cnt <= cnt + 1;
end if;
end if;
您在第一个elsif中对时钟沿进行了条件测试,该测试分配了cnt。 请注意,以下其他情况也分配了cnt而不考虑时钟沿。 这不是用于推断顺序边缘敏感逻辑的合成合格形式。
以下还有if语句,看起来可疑的综合资格:
if reset = '1' then
elsif pulsos ='0' then
if cnun = "1001" then
cnun <= "0000";
cndec <= cndec + 1;
if cndec = "1001" then
cndec <= "0000";
cncen <= cncen + 1;
if cncen = "1001" then
cncen< = "0000";
end if;
end if;
else
cnun <= cnun+1;
end if;
end if;
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