如何使FPGA在七段显示器上显示多（四）位？

Question

我有一个带有可附加键盘的Nexys 4 DDR FPGA。 FPGA应该在7段显示器上最多显示4个键盘按键，此后的任何按键都将取代最早的按键。

我有显示单个按键的代码，但不确定如何修改代码以在其他7段显示器上显示其他数字。

我是VHDL的新手； 我尝试将数字向左移动，然后在右侧简单地显示最新数字，但是遇到各种语法错误，例如尝试读取输出作为输入。

这是一位数字的功能代码。

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;

entity PmodKYPD_Nexsy4 is
    Port ( clk : in STD_LOGIC;
           JA : inout STD_LOGIC_VECTOR (7 downto 0);    -- PmodKYPD connected to Pmod JA
           an : out STD_LOGIC_VECTOR (7 downto 0);      -- Controls which position of the 8 seven segment displays to display
           seg: out STD_LOGIC_VECTOR (6 downto 0));     -- digit to display on seven segment display
end PmodKYPD_Nexsy4;

architecture Behavioral of PmodKYPD_Nexsy4 is
component Decoder is
    Port (
          clk : in  STD_LOGIC;
          Row : in  STD_LOGIC_VECTOR (3 downto 0);
          Col : out  STD_LOGIC_VECTOR (3 downto 0);
          DecodeOut : out  STD_LOGIC_VECTOR (3 downto 0));
    end component;

component DisplayController is
    Port (
           DispVal : in  STD_LOGIC_VECTOR (3 downto 0);
           anode:    out std_logic_vector(7 downto 0);
           segOut :  out  STD_LOGIC_VECTOR (6 downto 0));
    end component;

signal Decode: STD_LOGIC_VECTOR (3 downto 0);

begin
    C0: Decoder port map (clk=>clk, Row =>JA(7 downto 4), Col=>JA(3 downto 0), DecodeOut=> Decode);
    C1: DisplayController port map (DispVal=>Decode, anode=>an, segOut=>seg );

end Behavioral; 

---

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DisplayController is
    Port ( DispVal : in STD_LOGIC_VECTOR (3 downto 0);
           anode : out STD_LOGIC_VECTOR (7 downto 0);
           segOut : out STD_LOGIC_VECTOR (6 downto 0));
end DisplayController;

architecture Behavioral of DisplayController is

begin
    -- only display the rightmost digit, active low
    anode<="11111110";


     with DispVal select       -- active low to display segment
        segOut <=     "1000000" when "0000", --0
                      "1111001" when "0001", --1
                      "0100100" when "0010", --2
                      "0110000" when "0011", --3
                      "0011001" when "0100", --4
                      "0010010" when "0101", --5
                      "0000010" when "0110", --6
                      "1111000" when "0111", --7
                      "0000000" when "1000", --8
                      "0010000" when "1001", --9
                      "0001000" when "1010", --A
                      "0000011" when "1011", --B
                      "1000110" when "1100", --C
                      "0100001" when "1101", --D
                      "0001110" when "1110", --E
                      "0000110" when "1111", --F
                      "0111111" when others;

end Behavioral;

---

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Decoder is
    Port ( clk : in STD_LOGIC;
           Row : in STD_LOGIC_VECTOR (3 downto 0);
           Col : out STD_LOGIC_VECTOR (3 downto 0);
           DecodeOut : out STD_LOGIC_VECTOR (3 downto 0));
end Decoder;

architecture Behavioral of Decoder is
    signal sclk :STD_LOGIC_VECTOR(19 downto 0);
begin
    process(clk)
    begin
        if clk'event and clk = '1' then
            -- 1ms
            if sclk = "00011000011010100000" then 
                --C1
                Col<= "0111";
                sclk <= sclk+1;
            -- check row pins
            elsif sclk = "00011000011010101000" then    
                --R1
                if Row = "0111" then
                    DecodeOut <= "0001";    --1
                --R2
                elsif Row = "1011" then
                    DecodeOut <= "0100"; --4
                --R3
                elsif Row = "1101" then
                    DecodeOut <= "0111"; --7
                --R4
                elsif Row = "1110" then
                    DecodeOut <= "1111"; --F (mod from "0000"; --0)
                end if;
                sclk <= sclk+1;
            -- 2ms
            elsif sclk = "00110000110101000000" then    
                --C2
                Col<= "1011";
                sclk <= sclk+1;
            -- check row pins
            elsif sclk = "00110000110101001000" then    
                --R1
                if Row = "0111" then        
                    DecodeOut <= "0010"; --2
                --R2
                elsif Row = "1011" then
                    DecodeOut <= "0101"; --5
                --R3
                elsif Row = "1101" then
                    DecodeOut <= "1000"; --8
                --R4
                elsif Row = "1110" then
                    DecodeOut <= "0000"; --0 (mod from "1111"; --F)
                end if;
                sclk <= sclk+1; 
            --3ms
            elsif sclk = "01001001001111100000" then 
                --C3
                Col<= "1101";
                sclk <= sclk+1;
            -- check row pins
            elsif sclk = "01001001001111101000" then 
                --R1
                if Row = "0111" then
                    DecodeOut <= "0011"; --3    
                --R2
                elsif Row = "1011" then
                    DecodeOut <= "0110"; --6
                --R3
                elsif Row = "1101" then
                    DecodeOut <= "1001"; --9
                --R4
                elsif Row = "1110" then
                    DecodeOut <= "1110"; --E
                end if;
                sclk <= sclk+1;
            --4ms
            elsif sclk = "01100001101010000000" then            
                --C4
                Col<= "1110";
                sclk <= sclk+1;
            -- check row pins
            elsif sclk = "01100001101010001000" then 
                --R1
                if Row = "0111" then
                    DecodeOut <= "1010"; --A
                --R2
                elsif Row = "1011" then
                    DecodeOut <= "1011"; --B
                --R3
                elsif Row = "1101" then
                    DecodeOut <= "1100"; --C
                --R4
                elsif Row = "1110" then
                    DecodeOut <= "1101"; --D
                end if;
                sclk <= "00000000000000000000"; 
            else
                sclk <= sclk+1; 
            end if;
        end if;

    end process;

end Behavioral;

Answer 1

我同意另一条评论，那就是最好从示意图中找出需要做什么。

您到底尝试了什么？ 查看VHDL中的注释，看来您可能需要在DisplayController更改设置为'0'的anode位（以选择要使用的7段显示器）。 您可以首先尝试将anode所有位设置为零，以确认在所有7段显示器上看到相同的数字。

然后，您可能想知道如何在不同的7段显示器上同时显示不同的数字。 通常一次只驱动一个7段显示器，但是要在不同的显示器之间快速切换是一个常见的技巧，因此（在我们缓慢的人眼中）它们都同时点亮。