如何为我的fpga创建ClockSignal

Question

我的问题很简单，因为我在Xilinx sp605板上有一个200MHZ的时钟，并且由于我的设计只能在100Mhz上运行，所以我希望输入时钟为100Mhz，因此要实现这一点：请仅在UCF文件中写入时钟值就是这样，还是我必须创建一个需要200Mhz的VHDL组件并将其设为100Mhz？

这是mu ucf文件：

#  Spartan-6 SP605 Evaluation Platform
Net fpga_0_RS232_Uart_1_RX_pin LOC = H17  |IOSTANDARD=LVCMOS25;
Net fpga_0_RS232_Uart_1_TX_pin LOC = B21  |IOSTANDARD=LVCMOS25;
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<0> LOC=C18  |IOSTANDARD=LVCMOS25;
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<1> LOC=Y6  |IOSTANDARD=LVCMOS25;
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<2> LOC=W6  |IOSTANDARD=LVCMOS25;
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<3> LOC=E4  |IOSTANDARD=LVCMOS15;
NET LED<0> LOC = "D17"; ## 2 on DS3 LED
NET LED<1> LOC = "AB4"; ## 2 on DS4 LED
NET LED<2> LOC = "D21"; ## 2 on DS5 LED
NET LED<3> LOC = "W15"; ## 2 on DS6 LED
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=L20  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=P20  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=N15  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=T22  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=P19  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=Y22  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=Y21  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=W22  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=M16  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=U20  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC=J22  |IOSTANDARD = LVCMOS25  |TIG;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=T8  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=U10  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=T10  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=AB8  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=AA8  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_MDC_pin LOC=R19  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_MDIO_pin LOC=V20  |IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_MDINT_pin LOC=J20  |IOSTANDARD = LVCMOS25  |TIG;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<0> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<1> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<2> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<3> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<4> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<5> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<6> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<7> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<8> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<9> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<10> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<11> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<12> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ba_pin<0> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ba_pin<1> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ba_pin<2> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ras_n_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_cas_n_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_we_n_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_cke_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_clk_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_clk_n_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<0> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<1> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<2> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<3> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<4> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<5> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<6> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<7> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<8> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<9> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<10> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<11> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<12> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<13> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<14> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<15> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dqs_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dqs_n_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_udqs_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_udqs_n_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_udm_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ldm_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_odt_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ddr3_rst_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_rzq_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_zio_pin IOSTANDARD = SSTL15_II;
Net fpga_0_clk_1_sys_clk_p_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;
Net fpga_0_clk_1_sys_clk_p_pin LOC = K21  |IOSTANDARD=LVDS_25  |DIFF_TERM = TRUE;
Net fpga_0_clk_1_sys_clk_n_pin LOC = K22  |IOSTANDARD=LVDS_25  |DIFF_TERM = TRUE;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC = H8  |IOSTANDARD=LVCMOS15  |PULLUP  |TIG;

LOC K21和k22已被microblaze占用，我无法使用它们，甚至在文档中问题还是我无法获取全局时钟引脚和其频率（顺便说一句，我指的是此文档（ Xilinx硬件设计 ），以及为什么EDK ucf文件不包含DDR3引脚的LOC ??似乎工作正常，fpga可以自己解决吗！

编辑：好的，这里的图像来自gui计划，它显示了我的spartan 6中的所有I / O端口，因为您看到所有六边形都是GCLK（全局时钟），可以用作我的设计时钟，问题是我不知道每个时钟的频率是多少！

Answer 1

您不应该编写自己的时钟分频器。 您应该使用内部DCM，它实际上可以路由到全局时钟网络。 一种简单的方法是使用coregen工具，该工具可让您使用模板来实例化DCM。 您可以将时钟信号分频，乘法，相移等到合理范围内的几乎所有信号。 有关详细信息，请参见数据表。 如果仅将时钟分频（例如使用触发器），则时钟偏差会非常严重，并且很可能（几乎可以保证）遇到严重的计时问题。 您想利用fpga的时钟路由网络。

Answer 2

您必须编写一个预分频器才能将时钟除以2。（或者可能是2000，因为SP605时钟的频率是200MHz ，而不是200kHz ）

UCF文件中的值仅告诉ISE您现有外部时钟的频率，它不会自动为您生成该频率。