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Verilog - Calling a module inside a case statement

 原文  2016-01-19 12:52:37  6   2    verilog/ case-statement

Question

我对Verilog不太熟悉，但是在case语句中可以调用另一个模块吗？

2 answers

solution1
 2  2016-01-19 13:06:10

You cannot call a module just as you do in C language, since it's not a function, you instantiate it. If you want to instantiate a module, you should use generate .

Edit: An example of using generate with a case statement can be found here .

2nd edit: If you just wanted to call a section of code in a case-statement then you can create a task or a function . More information here . (credit goes to Hida )

solution2
 0  2016-02-05 12:06:34

您不能在case语句中调用模块，但是可以创建函数，然后再调用case语句（任务无法合成）

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