I want to selectively compile below code in system verilog:
always_comb begin
out = 0;
case(exp)
state_1: out = a*b;
state_2: out = b|c;
state_3: out = c^d;
endcase
end
Is this the right way of doing it? Will the state_3 code be removed in synthesis?
parameter PARAM_1 = 1'b1;
parameter PARAM_2 = 1'b1;
parameter PARAM_3 = 1'b0;
always_comb begin
out = 0;
case(exp)
state_1: if (PARAM_1 == 1'b1) out = a*b;
state_2: if (PARAM_2 == 1'b1) out = b|c;
state_3: if (PARAM_3 == 1'b1) out = c^d;
endcase
end
I want the output of the above code be like below after synthesis.
always_comb begin
out = 0;
case(exp)
state_1: out = a*b;
state_2: out = b|c;
endcase
end
Is there a way of doing the same using generate block? The below code won't work since there are multiple driver for out varaible in different block.
parameter PARAM_1 = 1'b1;
parameter PARAM_2 = 1'b1;
parameter PARAM_3 = 1'b0;
generate
if (PARAM_1 ==1'b1) begin
always_comb begin
case(exp)
state_1: out = a*b;
default : out = 0;
endcase
end
endgenerate
generate
if (PARAM_2 ==1'b1) begin
always_comb begin
case(exp)
state_1: out = b|c;
default : out = 0;
endcase
end
endgenerate
generate
if (PARAM_3 ==1'b1) begin
always_comb begin
case(exp)
state_1: out = c^d;
default : out = 0
endcase
end
endgenerate
There is no use of using a generate block for what you are trying to synthesize. Generate blocks are used best when you want to instantiate multiple modules.
Here is a good reference for understanding how you can use generate with case statements, but you can do this with simple for loop too.
https://www.verilogpro.com/verilog-generate-configurable-rtl/
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