Append/Substitute string in Makefile from another makefile

Question

I wanted to string substitute this one string in one of the .mak file my main Makefile includes, like so:

/boo.mak

[...]

LOADLIBES += -lGoo
LOADLIBES += -lBaa -lCov -lDtt  // -lDtt to be replaced

[...]

/Makefile

[...]

include $(DIR)/boo.mak

[...]

The -lDtt is to be replaced by something like -Wl, --do-something -lDtt -Wl --undo-something

How would you recommend to do this? I've tried this:

/test

[...]
replace:= -Wl, --do-something -lDtt -Wl --undo-something
dtt:= -lDtt
boo:= $(DIR)/boo.mak

newboo:= $(subst $(dtt),$(replace),$(boo))

include $(newboo)
[...]

But nothing changed, the -lDtt still exist and does not replace with the text I wanted after I run.

Edit: I'm using gcc and linux.

Answer 1

The third parameter to $(subst is the actual string to replace. It is not the name of the file where the string is found, as you seem to believe.

Example:

$ cat Makefile
replace:= -Wl, --do-something -lDtt -Wl --undo-something
dtt:= -lDtt
boo:= This string contains -lDtt which will be replaced

newboo:= $(subst $(dtt),$(replace),$(boo))

testme:
    echo $(newboo)
$ make testme
echo This string contains -Wl, --do-something -lDtt -Wl --undo-something which will be replaced
This string contains -Wl, --do-something -lDtt -Wl --undo-something which will be replaced

So, in your case, you will need to use the $(subst on the LOADLIBES variable, to replace its contents.

Answer 2

Okay, thanks to the above answer. I manage to get an insight of what was wrong and next steps I should take to make things work. Here is my current Makefile:

[...]

include $(DIR)/boo.mak

replace:= -Wl, --do-something -lDtt -Wl --undo-something
dtt:= -lDtt
boo:= $(subst $(dtt),$(replace),$(LOADLIBES))

LOADLIBES = $(boo) //replace old LOADLIBES variable with new modified lib

[...]

I'm open to any suggestion to make this better but it is working fine for now.