It's been years I've been working with verilog but recently I'm testing something with verilog. During a ncvlog compile, I have an error for which I can't find the cause. Below is the code(not complete yet).
`include "default.v"
module conv (
input clr,
input clk,
input start_conv,
output integer raddr,
output integer waddr,
input real data_in,
output real data_out
);
parameter NUM_CONV = `DEF_NUM_CONV;
genvar i;
generate
for (i=0; i<NUM_CONV; i=i+1) begin : uconv
unit_conv inst() (
.clr (clr),
.clk (clk),
.start (start_conv),
.rreq (rreq[i]),
.raddr (raddr[i]),
.rdata (rdata[i]),
.wreq (wreq[i]),
.waddr (waddr[i]),
.wdata (wdata[i])
);
end
endgenerate
endmodule
The error I get is like below :
ckim@stph45:~/Neuro/convhw] ncvlog -sv conv.v
ncvlog: 12.20-s008: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
unit_conv inst() (
|
ncvlog: *E,EXPSMC (conv.v,19|17): expecting a semicolon (';') [12.1.2][7.1(IEEE)].
Is the port mapping syntax for generated instances wrong? According to this it seems correct though... By the way, I compile with ncvlog -SV conv.v
.
Consider the following:
unit_conv inst (
.clr (clr),
.clk (clk),
.start (start_conv),
.rreq (rreq[i]),
.raddr (raddr[i]),
.rdata (rdata[i]),
.wreq (wreq[i]),
.waddr (waddr[i]),
.wdata (wdata[i])
);
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