Not getting simulated output for an error free verilog code

Question

I'm somewhat new to verilog. So this question might be very simple. I'm trying to simulate an finite state machine using verilog. Brief description: There are three states: 0,1 & 2. By default, State is 0. The state changes to 1 only if input is 01. The state changes to 2 only if input is 10. The state changes back to 0 only if input is 00. The code is getting simulated successfully, but Im getting no output. Please help me with the problem.

Code: (State.v)

module State(
    input clk,
    input reset,
     input [3:0] in,
     output [3:0] out,
     output [3:0] state
    );

     wire clk,reset;
     wire [3:0] in;
     reg [3:0] out;
     reg [3:0] state;

     always @(posedge clk or posedge reset)
      begin
      if (reset == 1)
        begin
            state = 0;
        end
      else 
        begin
            case (state)
                0: if(in == 2'b01)
                         state = 1;
                        else
                         state = 0;
                1: if(in == 2'b10) 
                        state = 2;
                      else
                       state = 1;
                2: if(in == 2'b00)
                        state = 0;
                      else
                       state = 2;
                default: state = 0;     
            endcase 
        end 
     end    

     always @(*)
        begin
            case (state)
                0: out = 2'b00;
                1: out = 2'b01;
                2: out = 2'b10;
                default: out = 2'b00;
            endcase     
        end     

endmodule

Testbench: (StateTestBench.v)

module StateTestBench;

    // Inputs
    reg clk;
    reg reset;
    reg [3:0] in;

    // Outputs
    reg [3:0] out;
    reg [3:0] state;

    always
        begin
            #1 clk = !clk;
        end 

    // Instantiate the Unit Under Test (UUT)
    State uut (
        .clk(clk), 
        .reset(reset), 
        .in(in),
        .out(out),
        .state(state) 
    );

    initial begin
        // Initialize Inputs
        clk = 0;
        reset = 0;

        #1 reset = 1;
        #10 reset = 0;
        #5 in = 2'b00;
        #10 in = 2'b01;
        #10 in = 2'b10;



    end

endmodule

Answer 1

I guess you simulate state.v instead of StateTestBench.v. Because your testbench has a bug! Outputs out and state MUST be wires.