Resetting the output of Verilog code

Question

This program displays S then off then G then off. The program works but the reset doesn't work perfectly. There is some error in the waveform. I know that the problem in the value in y when the clock comes, but I don't know how to solve it.

module proj200 (output wire [6:0]a2g,output wire [3:0]AN,input wire fastclk,input reset); 
wire slowclk;
wire y;
slow_clock xx(fastclk,slowclk);
yinput za(slowclk,y);
hex7segm zz(slowclk,y,reset,a2g,AN);
endmodule

module slow_clock (input wire fastclk,output wire slowclk);
reg[1:0]period_count=0;
always@(posedge fastclk)
begin

period_count<=period_count+1;

end
assign slowclk=period_count[1];

endmodule




module hex7segm (input wire slowclk,input wire y,input reset,
output reg [6:0]a2g,
output reg [3:0]AN
); 
reg[1:0]x;
always@(*)
begin
if(slowclk==1 && reset==0)
begin x=2;
AN= 4'b1110;
end
else if(slowclk==0 && reset==0)

    begin
x=y;
AN= 4'b1110;
end   

else if(reset==1&& slowclk==0)
    begin 

        x=0;
        AN= 4'b1110;
end

else if(reset==1 && slowclk==1) 
    begin 

        x=0;
        AN= 4'b1110;
        end


case(x)
0: a2g=7'b0100100;
1: a2g=7'b0100000;
2: a2g=7'b1111111;
default: a2g=7'b0100100;
endcase
end
endmodule


module yinput(input wire slowclk,output wire y);
reg[1:0]period_count=0;
always@(posedge slowclk )
begin

period_count<=period_count+1;

end
assign y=period_count[0];

endmodule

Answer 1

Your reset is currently doing nothing but masking the outputs (ie, forcing x and AN to some default value). It is doing nothing to your registers containing period_count (which in turn determines y and slowclk ). Now you need to determine if you want a synchronous (a reset that follows the clock) or asynchronous reset (a reset independent of the clock). Heres examples of both:

Synchronous

reg [1:0] period_count; // Dont need this initialization, a reset will do it for you
always @(posedge fastclk) begin
  if (reset)
    period_count <= 0;
  else
    period_count <= period_count+1;
end

Asynchronous

reg [1:0] period_count; // Dont need this initialization, a reset will do it for you
always @(posedge fastclk, posedge reset) begin // Note the new item in the sensitivity list
  if (reset)
    period_count <= 0;
  else
    period_count <= period_count+1;
end

Note that reset will have to become an input to your other modules and you can take reset out of the module its currently in as that module is just combinational. If you want some other behavior, you are going to have to clarify that.