Should I be able to see these in the generated VCD file? I can see all the signals I created at the top level, but not the ones local to the functi ...

The code added fails with a ValueError and i have no idea whats going wrong. Here is what i want to do: In my fpga i receive data via spi. Data is a b ...

I am trying to download myhld on ubuntu and also install the cosimulation. myhdl was installed fine but when following the cosimulation installation i ...

How to write myhdl code to implement Unary XOR in verilog doesn't work for me. ...

I'm a beginner with myhdl. I try to translate the following Verilog code to MyHDL: module ModuleA(data_in, data_out, clk); input data_in; out ...

From the code mostly from the sample of myhdl: I expect it to generate a verilog program that contains an initial block, like something: How c ...

I'm new to python and MyHDL so I started by converting old VHDL projects to MyHDL. This project is a vga timer that can accept any width, height, and ...

I am trying to setup myHDL with Python2 on Windows 10 in order to work with VHDL/Verilog testbenches using Python for the source code. The correspondi ...

I'm trying to learn MyHDL by writing a very simple machine with just a handful of instructions and operations. What I'm struggling with is the best wa ...

I am trying to generate a verilog module from the following MyHDL module: top.py: and, counter.py: However, in the generated file's module def ...

I'm trying to make a python library for dynamically making a UART interface between a PC and FPGA using pySerial using myHDL 1.0dev It takes names fo ...

I would like to do a sum of signals that I have in a list, naturally I have used variable and for (as I would in VHDL): The problem is that this wi ...

I will be using an iCE40HX8K given the evaluation boards constraint file whats the best way to bundle all 8 LED's into one variable I had trouble ...

I'm trying to convert this code to Verilog: however, i got the following error: Moving the variables inside the qwe function will work, but I ne ...

I have the following code in my myhdl environment: the above code doesn't work but when I replace it with the following it works: I am confused ...

I'm currently looking into myHdl to see if it's worth using or not. However, I've come across a hiccup regarding the instantiation of modules. I've go ...

I encountered this error when running a testbench, together with a synchronizer built on two existing D-FFs. My testbench is outlined as follows ...

I have tried the following code from myHDL manual on EDAPlayground.com, but it didn't print anything out for me. Can anyone show me why ? and how to s ...

Is there a way to specify library use clauses when using MyHDL user-defined code? Consider the following example, which models a differential buffer ...

Considering the following example (a simple 8-bit counter), is there a simpler way to connect the internal s_count signal to the o_count port? Of ...