How to write myhdl code to implement Unary XOR in verilog
reg [63:0] large_bus;
wire xor_value;
assign xor_value = ^large_bus;
doesn't work for me.
@block
def dataVecXor(large_bus, xor_value):
@always_comb
def outputlogic():
xor_value.next = ^large_bus
return instances()
There is a solution On MyHDL's issue tracker:
large_bus = Signal(intbv(0)[128:0])
xor_value = Signal(bool(0))
@always_comb
def beh_reduction_xor():
x = large_bus[0]
for ii in range(1, len(large_bus)):
x = x ^ large_bus[ii]
xor_value.next = x
You can construct what you want by using 'for'.
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