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Verilog XOR operation with “z” input

原文 2018-01-25 06:16:18 2 2 verilog

Say, I have a 4 bit test_expr formed by concatenating 4 1b input ports. The input port corresponding to the LSB of test_expr is connected at TB top with a wire but the wire is undriven.

I have an assert that fires if(^test_expr === 1'bx). I am using Synopsys VCS and Verdi to simulate my design.

Now when i pull out the test_expr in verdi, i see a "z" on LSB. And my assert also fires.

Does this mean that XOR operation with a "z" bit always gives out an "x"? Or is this something that is simulator dependent and can vary?

Thanks

2 answers

Does this mean that XOR operation with a "z" bit always gives out an "x"?

Yes. Inputs to logic gates must always be driven; a floating ("z") input to a gate will result in erroneous, unpredictable behavior ("x").

The xor operation gives an output of x when any of the inputs is z . Please find the truth table for the basic gate operations here . As Matthew Taylor has pointed out in a previous comment, that is logically the correct output for a floating input.
As to give an answer to your comment, Z means 'high impedance'. Hence when any of the inputs is not clear (be it an X or Z), we can only expect the result to be unknown 'x' and not 'z'.

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Verilog XOR operation with “z” input

Question

2 answers

solution1
2 2018-01-25 06:38:08

solution2
0 ACCPTED 2018-01-25 10:01:25

Verilog XOR operation with “z” input

Question

2 answers

solution1 2 2018-01-25 06:38:08

solution2 0 ACCPTED 2018-01-25 10:01:25

solution1
2 2018-01-25 06:38:08

solution2
0 ACCPTED 2018-01-25 10:01:25