MyHDL: library use clauses in user-defined code

Question

Is there a way to specify library use clauses when using MyHDL user-defined code?

Consider the following example, which models a differential buffer that is available in the Xilinx unisim library:

from myhdl import *

def ibufds(I, IB, O):
    """ Xilinx Differential Signaling Input Buffer"""
    @always_comb
    def output():
        O.next = I        
    return instances()

ibufds.vhdl_code = """    
IBUFDS_inst : IBUFDS
generic map (
    DIFF_TERM => FALSE,
    IBUF_LOW_PWR => TRUE,referenced I/O standards
    IOSTANDARD => "DEFAULT")
port map (
    O => O,
    I => I,
    IB => IB
);"""

Converting this module to VHDL code works fine, but what is missing is the following use clause in the header of the VHDL file:

library unisim;
use unisim.vcomponents.all;

How can I fix that?

Answer 1

Yes, toVHDL() supports a use_clauses attribute. This can hold a (possibly multiline) string that will be inserted at the appropriate location. This is just inserted, so you can also add library declarations.

This is supported, but I noticed I forgot to add it to the documentation - needs to be fixed.

Currently, when using this attribute, the pck_myhdl* use declaration is omitted - I used use_clauses in projects where another name for that package was desired. This looks slightly confusing, perhaps it would be better to keep that functionality separate using a different parameter.