[英]MyHDL: library use clauses in user-defined code
Is there a way to specify library use clauses when using MyHDL user-defined code? 使用MyHDL用户定义的代码时,是否可以指定库使用子句?
Consider the following example, which models a differential buffer that is available in the Xilinx unisim library: 考虑以下示例,该示例对Xilinx unisim库中可用的差分缓冲器进行建模:
from myhdl import *
def ibufds(I, IB, O):
""" Xilinx Differential Signaling Input Buffer"""
@always_comb
def output():
O.next = I
return instances()
ibufds.vhdl_code = """
IBUFDS_inst : IBUFDS
generic map (
DIFF_TERM => FALSE,
IBUF_LOW_PWR => TRUE,referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => O,
I => I,
IB => IB
);"""
Converting this module to VHDL code works fine, but what is missing is the following use clause in the header of the VHDL file: 将此模块转换为VHDL代码可以正常工作,但缺少的是VHDL文件头中的以下use子句:
library unisim;
use unisim.vcomponents.all;
How can I fix that? 我该如何解决?
Yes, toVHDL()
supports a use_clauses
attribute. 是的,
toVHDL()
支持use_clauses
属性。 This can hold a (possibly multiline) string that will be inserted at the appropriate location. 这可以包含一个(可能是多行)字符串,该字符串将插入到适当的位置。 This is just inserted, so you can also add library declarations.
这只是插入的,因此您还可以添加库声明。
This is supported, but I noticed I forgot to add it to the documentation - needs to be fixed. 这是受支持的,但是我注意到我忘记将其添加到文档中-需要修复。
Currently, when using this attribute, the pck_myhdl*
use declaration is omitted - I used use_clauses
in projects where another name for that package was desired. 当前,当使用此属性时,将省略
pck_myhdl*
use声明-我在需要该软件包另一个名称的项目中使用过use_clauses
。 This looks slightly confusing, perhaps it would be better to keep that functionality separate using a different parameter. 这看起来有些混乱,也许最好使用不同的参数将功能分开。
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