[英]Connect internal signal to output port in MyHDL module
Considering the following example (a simple 8-bit counter), is there a simpler way to connect the internal s_count
signal to the o_count
port? 考虑以下示例(一个简单的8位计数器),是否有更简单的方法将内部s_count
信号连接到o_count
端口?
def counter(i_clk, i_reset, o_count):
""" A free-running 8-bit counter with a synchronous reset """
s_count = Signal(intbv(0)[8:])
@always(i_clk.posedge)
def count():
if i_reset == 1:
s_count.next = 0
else:
s_count.next = s_count + 1
@always_comb
def outputs():
o_count.next = s_count
return count, outputs
Of course, I could directly increment o_count
in the count
function but this translates to an inout
port in the generated VHDL module, which I don't want. 当然,我可以直接在count
函数中增加o_count
,但这会转换为生成的VHDL模块中的inout
端口,我不需要。
I suspect directly incrementing o_count is an acceptable solution. 我怀疑直接增加o_count是可以接受的解决方案。
Indeed, it translates to an inout because you cannot read output ports in VHDL. 实际上,它转换为输入,因为您无法读取VHDL中的输出端口。
However, this will only happen when you convert this module as a top module. 但是,仅当将此模块转换为顶部模块时,才会发生这种情况。 It is likely that this is a small submodule however. 但是,这可能是一个小的子模块。 In that case, the hierarchy is flattened out and o_count will be an internal signal. 在这种情况下,层次结构被展平,而o_count将是一个内部信号。
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