Verilog simulation errors

Question

In the simulation, 'a' won't be change its value and I can't seem to know why. 'carry out(co)' always comes out as HiZ, and the 'sum' creates a bit weird values. 'of(overflow)' value as well Can anybody help me out with this? Any help will be appreciated. Thanks a lot in advance.

    `timescale 100ps/1ps    
module RCA_tb;
reg [7:0] a;
reg [7:0] b;
reg ci;
wire [7:0] sum;
wire co;
wire of; //overflow
integer i;

RippleCA RCA(a,b,ci,sum,co,of); 

initial begin 

    a=0;
    b=0;
    ci=0;

    end



    initial begin // all possible cases 

    for(i=0; i<256; i=i+1)


    #10 {a, b, ci} = i;


    end
endmodule

module RippleCA(a,b,ci,sum,co,of);
input [7:0] a;
input [7:0] b;
input ci;
output [7:0] sum;
output co;
output of;
wire[6:0] c;
FullAdder a1(a[0],b[0],ci,sum[0],c[0]);
FullAdder a2(a[1],b[1],c[0],sum[1],c[1]);
FullAdder a3(a[2],b[2],c[1],sum[2],c[2]);
FullAdder a4(a[3],b[3],c[2],sum[3],c[3]);
FullAdder a5(a[4],b[4],c[3],sum[4],c[4]);
FullAdder a6(a[5],b[5],c[4],sum[5],c[5]);
FullAdder a7(a[6],b[6],c[5],sum[6],c[6]);
FullAdder a8(a[7],b[7],c[6],sum[7],cout);
xor x2(of,c[6],co); //overflow detection
endmodule
module FullAdder (
a,b,ci,sum,co
);
input a,b,ci;
output sum,co;
wire w1, w2, w3;
xor x1(sum, a, b, ci);
and a1(w1,a,b);
and a2(w2,b,ci);
and a3(w3,ci,a);
or o1(co,w1,w2,w3);
endmodule

This is my Verilog code.

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Answer 1

You declared

reg [7:0] a;
reg [7:0] b;
reg ci;

And assigned

{a, b, ci} = i;

{a,b,ci} is 17 bits wide but you are counting i to up to 255 which is 8 bits wide, in this case a will always be zero. If you increase your for loop to for(i=0; i<262144; i=i+1) you should be able to test it.