Alternate signals for test bench without manually typing out all times in iverilog

Question

I am writing a test bench that I want to be able to have signals go high and low in a certain pattern (something like this): Currently I manually type out what I want each time to be like this:

module TestExample;
reg a, b, c;

initial begin
    $dumpfile("test.vcd");
    $dumpvars(0, TestExample);

    # 0 a=0; b=0; c=0;
    # 10 a=1; b=0; c=0;
    # 20 a=0; b=1; c=0;
    # 30 a=1; b=1; c=0;
    # 40 a=0; b=0; c=1;
    # 50 a=1; b=0; c=1;
    # 60 a=0; b=1; c=1;
    # 70 a=1; b=1; c=1;
    # 80 a=0; b=0; c=0;

    # 90 $stop;
end
endmodule

The problem with this is when I get more signals (lets say az instead of ab) it will take a really long time to manually type out each time and the associated value. Because of this I am wondering if there is a way I can automate the signals. For example if I could say switch your state every 10 u-seconds for a, every 20 u-seconds for b, and every 30 u-seconds for c?

Answer 1

As Greg says...

module TestExample;
wire a, b, c, d ...
integer i;

initial begin
    $dumpfile("test.vcd");
    $dumpvars(0, TestExample);
    for (i = 0; i < 1<<26; i=i+1)
        #10;
    $stop;
end

assign a = i[0], b = i[1], c = i[2], d = i[3] ... 

endmodule

Answer 2

for generic patterns, you can use multiple initial blocks, say one per variable:

initial begin
   a = 0;
   forever begin
      #10 a = 1;
      #10 a = 0;
   end
end
initial
   b = 1;
   forever begin
      #30 b = 0;
      #30 b = 1;
   end
end
...
initial begin
    $dumpfile("test.vcd");
    $dumpvars(0, TestExample);

    #1000 $finish;
end