So, I have been racking my brain on this issue with the latest version of Mojo-IDE v1.3.6
Below is a short snippet of my code. As you can see I am attempting to use a generate with a for loop to create many instances of the 'Hashers' Block.
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
wire [511:0] W;
wire [255:0] state;
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
However, I get the following error when i try to synthesize:
Line 89, Column 38 : extraneous input '.' expecting {')', '[', '<=', '*', '+', '-', '?', '&', '|', '^', '~^', '^~', '/', '%', '==', '!=', '===', '!==', '&&', '||', '**', '<', '>', '>=', '>>', '<<', '>>>', '<<<'}
Line 90, Column 46 : extraneous input '.' expecting {')', '[', '<=', '*', '+', '-', '?', '&', '|', '^', '~^', '^~', '/', '%', '==', '!=', '===', '!==', '&&', '||', '**', '<', '>', '>=', '>>', '<<', '>>>', '<<<'}
The errors are on lines
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
According to Verilog-2000 guidelines this should be a legal as I should be able to access previous index of 'HASHERS' to obtain the 'W' bits for rx_w.
Any help would be much appreciated.
Regards, S
I tried it with vcs and it did not produce any issue with this code. So, it looks like your verilog compiler has issues with generate blocks.
I suggest to move your W
and state
declarations outside the block as the following:
wire [511:0] W[64/LOOP-1:0];
wire [255:0] state[64/LOOP-1:0];
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W[I] : rx_input),
.rx_state(feedback ? state[i] : rx_state),
.tx_w(W[i]),
.tx_state(state[i])
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W[i] : W[i-1]),
.rx_state(feedback ? state[i] : state[i-1]),
.tx_w(W[i]),
.tx_state(state[i])
);
end
endgenerate
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