Chisel memories support read masks directly?

Question

I have learned Chisel memories in Chisel Wiki page. It states that Chisel memories support write masks for subword writes. My question is that can Chisel memories support read masks for subword read directly? ig:

// Create a 32-bit wide memory that is byte-masked.     
   val mem = SyncReadMem(1024, Vec(4, UInt(8.W)))

   mem.write(writeAddr, dataIn, mask)
   dataOut := mem.read(readAddr, enable, mask)

Can it mask the data when mem reads directly as above? Or it must with another AND operation? ig:

dataOut := mem.read(readAddr, enable) & mask

Answer 1

Sorry, the chisel API for read on a SyncReadMem does not support

   dataOut := mem.read(readAddr, enable, mask)

I'm not sure why. I'll dig a bit and see if there's a reason.